SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Table 5-10 shows configuration pins assignment to functions when boot mode is QSPI using the OSPI module. The BOOTMODE pin corresponding to the Iclk field determines the setting for LOOPCLK_SEL bit field in CTRLMMR_OSPI0_CLKSEL register
| BOOTMODE Pins | Field | Value | Description |
|---|---|---|---|
| 8 | Iclk | 0 | Iclock source external |
| 1 | Iclock source internal (pad loopback) | ||
| 7 | Csel | 0 | Boot Flash is on CS 0 |
| 1 | Boot Flash is on CS 1 |
Table 5-11 summarizes the OSPI pin configuration done by ROM code for QSPI boot device on port 0.
| Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Strength Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
|---|---|---|---|---|---|---|---|
| OSPI0_CLK | OSPI0_CLK | Disable | NA | 0 | Disable | 0 | PADCONFIG0 |
| OSPI0_LBCLKO | OSPI0_LBCLKO | Disable | NA | 0 | Enable | 0 | PADCONFIG1 |
| OSPI0_DQS | OSPI0_DQS | Disable | NA | 0 | Enable | 0 | PADCONFIG2 |
| OSPI0_D0 | OSPI0_D0 | Disable | NA | 0 | Enable | 0 | PADCONFIG3 |
| OSPI0_D1 | OSPI0_D1 | Disable | NA | 0 | Enable | 0 | PADCONFIG4 |
| OSPI0_D2 | OSPI0_D2 | Disable | NA | 0 | Enable | 0 | PADCONFIG5 |
| OSPI0_D3 | OSPI0_D3 | Disable | NA | 0 | Enable | 0 | PADCONFIG6 |
| OSPI0_CSn0(1) | OSPI0_CSn0 | Disable | NA | 0 | Disable | 0 | PADCONFIG11 |
| OSPI0_CSn1(1) | OSPI0_CSn1 | Disable | NA | 0 | Disable | 0 | PADCONFIG12 |