SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| CPSW0 | ✓ |
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| CPSW0 | PSC0 | PD_CPSW | LPSC_CPSW3G | 41 | OFF | YES | LPSC_main_IP |
| Module Instance | Module Clock Input | Source Clock | Source Control Register | Description |
|---|---|---|---|---|
| CPSW0 | CPPI_ICLK | MAIN_SYSCLK0/2 | cppi streaming packet interface clock | |
| CPSW0 | CPTS_RFT_CLK | MAIN_PLL2_HSDIV5_CLKOUT | MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL[2:0]=0 | cpts reference clock |
| CPSW0 | CPTS_RFT_CLK | MAIN_PLL0_HSDIV6_CLKOUT | MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL[2:0]=1 | cpts reference clock |
| CPSW0 | CPTS_RFT_CLK | CP_GEMAC_CPTS_REF_CLK | MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL[2:0]=2 | cpts reference clock |
| CPSW0 | CPTS_RFT_CLK | MCU_EXT_REFCLK0 | MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL[2:0]=4 | cpts reference clock |
| CPSW0 | CPTS_RFT_CLK | EXT_REFCLK1 | MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL[2:0]=5 | cpts reference clock |
| CPSW0 | CPTS_RFT_CLK | MCU_SYSCLK0 | MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL[2:0]=6 | cpts reference clock |
| CPSW0 | CPTS_RFT_CLK | MAIN_SYSCLK0 | MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL[2:0]=7 | cpts reference clock |
| CPSW0 | GMII1_MR_CLK | MAIN_PLL2_HSDIV1_CLKOUT/10 | gmii input receive reference clock | |
| CPSW0 | GMII1_MT_CLK | MAIN_PLL2_HSDIV1_CLKOUT/10 | gmii input transmit reference clock | |
| CPSW0 | GMII2_MR_CLK | MAIN_PLL2_HSDIV1_CLKOUT/10 | gmii input receive reference clock | |
| CPSW0 | GMII2_MT_CLK | MAIN_PLL2_HSDIV1_CLKOUT/10 | gmii input transmit reference clock | |
| CPSW0 | GMII_RFT_CLK | MAIN_PLL2_HSDIV1_CLKOUT/2 | gmii input 125-mhz reference clock | |
| CPSW0 | RGMII_MHZ_250_CLK | MAIN_PLL2_HSDIV1_CLKOUT | rgmii 250-mhz reference clock | |
| CPSW0 | RGMII_MHZ_50_CLK | MAIN_PLL2_HSDIV1_CLKOUT/5 | rgmii 50-mhz reference clock | |
| CPSW0 | RGMII_MHZ_5_CLK | MAIN_PLL2_HSDIV1_CLKOUT/50 | rgmii 5-mhz reference clock | |
| CPSW0 | RMII1_MHZ_50_CLK | RMII1_REF_CLK (PIN) | rmii 50-mhz reference clock | |
| CPSW0 | RMII2_MHZ_50_CLK | RMII2_REF_CLK (PIN) | rmii 50-mhz reference clock |
| Module Instance | Source | Description |
|---|---|---|
| CPSW0 | PSC0 | CPSW0 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| CPSW0 | CPSW0_cpts_comp_0 | PINFUNCTION_CP_GEMAC_CPTS0_TS_COMPout_CP_GEMAC_CPTS0_TS_COMP_0 | PINFUNCTION_CP_GEMAC_CPTS0_TS_COMPout | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_cpts_comp_0 | CMP_EVENT_INTROUTER0_in_24 | CMP_EVENT_INTROUTER0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_cpts_genf0_0 | TIMESYNC_EVENT_ROUTER0_in_16 | TIMESYNC_EVENT_ROUTER0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_cpts_genf1_0 | TIMESYNC_EVENT_ROUTER0_in_17 | TIMESYNC_EVENT_ROUTER0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_cpts_sync_0 | PINFUNCTION_CP_GEMAC_CPTS0_TS_SYNCout_CP_GEMAC_CPTS0_TS_SYNC_0 | PINFUNCTION_CP_GEMAC_CPTS0_TS_SYNCout | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_cpts_sync_0 | TIMESYNC_EVENT_ROUTER0_in_18 | TIMESYNC_EVENT_ROUTER0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_ecc_ded_pend_0 | ESM0_esm_lvl_event_67 | ESM0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_ecc_sec_pend_0 | ESM0_esm_lvl_event_3 | ESM0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_evnt_pend_0 | GICSS0_spi_134 | GICSS0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_evnt_pend_0 | WKUP_R5FSS0_CORE0_intr_134 | WKUP_R5FSS0_CORE0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_mdio_pend_0 | GICSS0_spi_135 | GICSS0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_mdio_pend_0 | WKUP_R5FSS0_CORE0_intr_135 | WKUP_R5FSS0_CORE0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_stat_pend_0 | GICSS0_spi_136 | GICSS0 | CPSW0 interrupt request | level |
| CPSW0 | CPSW0_stat_pend_0 | WKUP_R5FSS0_CORE0_intr_136 | WKUP_R5FSS0_CORE0 | CPSW0 interrupt request | level |