SPRUIV7C May 2022 – November 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The PRU core can write and read data packets to and from port queues, located in the MSMC SRAM into PRU core registers via XFR2VBUS hardware accelerator. Each of the PRUSS Slices has implemented two RX XFR2VBUS hardware accelerators.
Supported features:
XFR2VBUS RX buffer features:
The ownership of commands and data is flexible. The XFR2VBUS accelerator is shared between PRU cores. Status is available to both cores.
Note: The ownership should be preplanned and static per use model.
The XFR2VBUS is a simple hardware accelerator wich is used to get the lowest read round trip latency from MSMC and to decouple the latency seen by the PRU. Each XFR2VBUS instance is connected to the CBASS0.
The PRUSS system has a total of 2 XFR2VBUS RX hardware accelerators.