SPRUJ09D March   2022  – September 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Control Card Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 HSEC 180-pin Control Card Docking Station
    5. 3.5 Compliance
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
      4. 4.1.4 Power Sequence
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
    4. 4.4 JTAG Path Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 RGMII
      2. 5.6.2 PRU-ICSS
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 HSEC Pinout and Pinmux Mapping
  8. 5References
    1. 6.1 References
    2. 6.2 Other TI Components Used in This Design
  9.   Revision History
  10.   A E2 Design Changes
  11.   B E1 HSEC Pinout Table

4.4 Clock

The AM263x SoC requires a 25-MHz clock input for XTAL_XI. All reference clocks required for the SoC and the three Ethernet PHY's are generated from a single four output clock buffer (LMK1C1104PWR), which is sourced from a single 25-MHz LVCMOS Oscillator by default. A clock buffer is used for level translation from 3.3 V to 1.8 V.

The Control Card also requires a 16-MHz clock source for the TM4C129 microcontroller for UART-USB JTAG support.

GUID-20220419-SS0I-HDF4-LJW0-6BZVWLFZPDBF-low.png Figure 4-5 Oscillator Clock Tree

Alternatively, the SoC clock input can be sourced from a single 25-MHz crystal. To use the crystal there must be resistors mounted and unmounted. When the Crystal is used as a clock source then the AM263x CLKOUT0 signal is used to source the four output clock buffer for the Ethernet PHY reference clock signals.

GUID-20220419-SS0I-ZKT2-NWS7-FW6NLCNBMFQ1-low.png Figure 4-6 Crystal Clock Tree

The following table describes the proper resistors to be mounted and DNI'd in order for each clock source configuration.

Table 4-2 Clock Source
Clock Source Mounted DNI
25-MHz LVCMOS Oscillator (default) R161, R135 R158, R155, R134
25-MHz Crystal R158, R155, R134 R161, R135