SPRUJD4A December 2024 – November 2025 AM62D-Q1
| Instance | MAIN | MCU | WKUP |
|---|---|---|---|
| DMASS0_INTAGGR_0 | ✓ |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_0 | GICSS0_spi_64 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_0 | C7X256V0_CLEC_gic_spi_32 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_1 | GICSS0_spi_65 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_1 | C7X256V0_CLEC_gic_spi_33 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_2 | GICSS0_spi_66 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_2 | C7X256V0_CLEC_gic_spi_34 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_3 | GICSS0_spi_67 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_3 | C7X256V0_CLEC_gic_spi_35 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_4 | GICSS0_spi_68 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_4 | C7X256V0_CLEC_gic_spi_36 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_5 | GICSS0_spi_69 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_5 | C7X256V0_CLEC_gic_spi_37 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_6 | GICSS0_spi_70 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_6 | C7X256V0_CLEC_gic_spi_38 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_7 | GICSS0_spi_71 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_7 | C7X256V0_CLEC_gic_spi_39 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_8 | GICSS0_spi_72 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_8 | C7X256V0_CLEC_gic_spi_40 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_9 | GICSS0_spi_73 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_9 | C7X256V0_CLEC_gic_spi_41 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_10 | GICSS0_spi_74 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_10 | C7X256V0_CLEC_gic_spi_42 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_11 | GICSS0_spi_75 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_11 | C7X256V0_CLEC_gic_spi_43 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_12 | GICSS0_spi_76 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_12 | C7X256V0_CLEC_gic_spi_44 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_13 | GICSS0_spi_77 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_13 | C7X256V0_CLEC_gic_spi_45 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_14 | GICSS0_spi_78 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_14 | C7X256V0_CLEC_gic_spi_46 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_15 | GICSS0_spi_79 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_15 | C7X256V0_CLEC_gic_spi_47 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_16 | GICSS0_spi_80 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_16 | C7X256V0_CLEC_gic_spi_48 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_17 | GICSS0_spi_81 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_17 | C7X256V0_CLEC_gic_spi_49 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_18 | GICSS0_spi_82 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_18 | C7X256V0_CLEC_gic_spi_50 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_19 | GICSS0_spi_83 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_19 | C7X256V0_CLEC_gic_spi_51 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_20 | GICSS0_spi_84 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_20 | C7X256V0_CLEC_gic_spi_52 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_21 | GICSS0_spi_85 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_21 | C7X256V0_CLEC_gic_spi_53 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_22 | GICSS0_spi_86 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_22 | C7X256V0_CLEC_gic_spi_54 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_23 | GICSS0_spi_87 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_23 | C7X256V0_CLEC_gic_spi_55 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_24 | GICSS0_spi_88 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_24 | C7X256V0_CLEC_gic_spi_56 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_25 | GICSS0_spi_89 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_25 | C7X256V0_CLEC_gic_spi_57 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_26 | GICSS0_spi_90 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_26 | C7X256V0_CLEC_gic_spi_58 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_27 | GICSS0_spi_91 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_27 | C7X256V0_CLEC_gic_spi_59 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_28 | GICSS0_spi_92 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_28 | C7X256V0_CLEC_gic_spi_60 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_29 | GICSS0_spi_93 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_29 | C7X256V0_CLEC_gic_spi_61 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_30 | GICSS0_spi_94 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_30 | C7X256V0_CLEC_gic_spi_62 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_31 | GICSS0_spi_95 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_31 | C7X256V0_CLEC_gic_spi_63 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_32 | GICSS0_spi_96 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_32 | C7X256V0_CLEC_gic_spi_64 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_33 | GICSS0_spi_97 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_33 | C7X256V0_CLEC_gic_spi_65 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_34 | GICSS0_spi_98 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_34 | C7X256V0_CLEC_gic_spi_66 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_35 | GICSS0_spi_99 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_35 | C7X256V0_CLEC_gic_spi_67 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_36 | GICSS0_spi_100 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_36 | C7X256V0_CLEC_gic_spi_68 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_37 | GICSS0_spi_101 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_37 | C7X256V0_CLEC_gic_spi_69 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_38 | GICSS0_spi_102 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_38 | C7X256V0_CLEC_gic_spi_70 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_39 | GICSS0_spi_103 | GICSS0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_39 | C7X256V0_CLEC_gic_spi_71 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_40 | WKUP_R5FSS0_CORE0_intr_64 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_41 | WKUP_R5FSS0_CORE0_intr_65 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_42 | WKUP_R5FSS0_CORE0_intr_66 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_43 | WKUP_R5FSS0_CORE0_intr_67 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_44 | WKUP_R5FSS0_CORE0_intr_68 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_45 | WKUP_R5FSS0_CORE0_intr_69 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_46 | WKUP_R5FSS0_CORE0_intr_70 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_47 | WKUP_R5FSS0_CORE0_intr_71 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_48 | WKUP_R5FSS0_CORE0_intr_72 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_49 | WKUP_R5FSS0_CORE0_intr_73 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_50 | WKUP_R5FSS0_CORE0_intr_74 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_51 | WKUP_R5FSS0_CORE0_intr_75 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_52 | WKUP_R5FSS0_CORE0_intr_76 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_53 | WKUP_R5FSS0_CORE0_intr_77 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_54 | WKUP_R5FSS0_CORE0_intr_78 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_55 | WKUP_R5FSS0_CORE0_intr_79 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_56 | WKUP_R5FSS0_CORE0_intr_80 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_57 | WKUP_R5FSS0_CORE0_intr_81 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_58 | WKUP_R5FSS0_CORE0_intr_82 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_59 | WKUP_R5FSS0_CORE0_intr_83 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_60 | WKUP_R5FSS0_CORE0_intr_84 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_61 | WKUP_R5FSS0_CORE0_intr_85 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_62 | WKUP_R5FSS0_CORE0_intr_86 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_63 | WKUP_R5FSS0_CORE0_intr_87 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_64 | WKUP_R5FSS0_CORE0_intr_88 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_65 | WKUP_R5FSS0_CORE0_intr_89 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_66 | WKUP_R5FSS0_CORE0_intr_90 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_67 | WKUP_R5FSS0_CORE0_intr_91 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_68 | WKUP_R5FSS0_CORE0_intr_92 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_69 | WKUP_R5FSS0_CORE0_intr_93 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_70 | WKUP_R5FSS0_CORE0_intr_94 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_71 | WKUP_R5FSS0_CORE0_intr_95 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_72 | WKUP_R5FSS0_CORE0_intr_8 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_73 | WKUP_R5FSS0_CORE0_intr_9 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_74 | WKUP_R5FSS0_CORE0_intr_10 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_75 | WKUP_R5FSS0_CORE0_intr_11 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_76 | WKUP_R5FSS0_CORE0_intr_12 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_77 | WKUP_R5FSS0_CORE0_intr_13 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_78 | WKUP_R5FSS0_CORE0_intr_14 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_79 | WKUP_R5FSS0_CORE0_intr_15 | WKUP_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_84 | C7X256V0_CLEC_soc_events_in_16 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_85 | C7X256V0_CLEC_soc_events_in_17 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_86 | C7X256V0_CLEC_soc_events_in_18 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_87 | C7X256V0_CLEC_soc_events_in_19 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_88 | C7X256V0_CLEC_soc_events_in_20 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_89 | C7X256V0_CLEC_soc_events_in_21 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_90 | C7X256V0_CLEC_soc_events_in_22 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_91 | C7X256V0_CLEC_soc_events_in_23 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_92 | C7X256V0_CLEC_soc_events_in_24 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_93 | C7X256V0_CLEC_soc_events_in_25 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_94 | C7X256V0_CLEC_soc_events_in_26 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_95 | C7X256V0_CLEC_soc_events_in_27 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_96 | C7X256V0_CLEC_soc_events_in_28 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_97 | C7X256V0_CLEC_soc_events_in_29 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_98 | C7X256V0_CLEC_soc_events_in_30 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_99 | C7X256V0_CLEC_soc_events_in_31 | C7X256V0_CLEC | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_168 | MCU_R5FSS0_CORE0_cpu0_intr_64 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_169 | MCU_R5FSS0_CORE0_cpu0_intr_65 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_170 | MCU_R5FSS0_CORE0_cpu0_intr_66 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_171 | MCU_R5FSS0_CORE0_cpu0_intr_67 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_172 | MCU_R5FSS0_CORE0_cpu0_intr_68 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_173 | MCU_R5FSS0_CORE0_cpu0_intr_69 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_174 | MCU_R5FSS0_CORE0_cpu0_intr_70 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_175 | MCU_R5FSS0_CORE0_cpu0_intr_71 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_176 | MCU_R5FSS0_CORE0_cpu0_intr_72 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_177 | MCU_R5FSS0_CORE0_cpu0_intr_73 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_178 | MCU_R5FSS0_CORE0_cpu0_intr_74 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_179 | MCU_R5FSS0_CORE0_cpu0_intr_75 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_180 | MCU_R5FSS0_CORE0_cpu0_intr_76 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_181 | MCU_R5FSS0_CORE0_cpu0_intr_77 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_182 | MCU_R5FSS0_CORE0_cpu0_intr_78 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |
| DMASS0_INTAGGR_0 | DMASS0_INTAGGR_0_intaggr_vintr_pend_183 | MCU_R5FSS0_CORE0_cpu0_intr_79 | MCU_R5FSS0_CORE0 | DMASS0_INTAGGR_0 interrupt request | level |