SPRZ193T January   2003  – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

 

  1.   1
  2. 1Introduction
  3. 2Device and Development Tool Support Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
  6. 5Known Design Exceptions to Functional Specifications
    1.     Advisory
    2.     Advisory
    3.     Advisory
    4.     Advisory
    5.     Advisory
    6.     Advisory
    7.     Advisory
    8.     Advisory
    9.     Advisory
    10.     Advisory
    11.     Advisory
    12.     Advisory
    13.     Advisory
    14.     Advisory
    15.     Advisory
    16.     Advisory
    17.     Advisory
    18.     Advisory
    19.     Advisory
    20.     Advisory
    21.     Advisory
    22.     Advisory
    23.     Advisory
    24.     Advisory
    25.     Advisory
    26.     Advisory
    27.     Advisory
    28.     Advisory
    29.     Advisory
    30.     Advisory
    31.     Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

5 Known Design Exceptions to Functional Specifications

Table 5-1 shows which silicon revision(s) are affected by each advisory.

Table 5-1 List of Advisories
TITLE SILICON REVISION(S) AFFECTED(1)
0 A B C D E F G
Memory: Prefetching Beyond Valid Memory Y Y Y Y Y Y Y Y
Memory: Program Reads From Flash/ROM Memory Y Y Y Y Y Y Y Y
Memory: Flash and OTP Prefetch Buffer Overflow Y Y Y Y Y Y Y Y
Memory: Set Device Emulation Register Bits for On-Chip RAM Performance Y Y N/A N/A N/A N/A N/A N/A
Memory: OTP Memory Y Y N/A N/A N/A N/A N/A N/A
XINTF: XBANK Does Not Properly Extend an Access Y Y Y Y Y Y Y Y
XINTF: XREADY Signal is not Sampled Properly When Using Asynchronous Sampling Mode Y Y N/A N/A N/A N/A N/A N/A
SCI: Incorrect Operation of SCI in Address Bit Mode Y Y Y Y Y Y Y Y
SCI: Bootloader Does Not Clear the ABD Bit After Auto-Baud Lock Y Y Y Y Y Y Y Y
SCI: Bootloader Does Not Clear the ABD Bit Before Auto-Baud Lock Y Y Y Y Y Y Y Y
eCAN: Abort Acknowledge Bit Not Set Y Y Y Y Y Y Y Y
eCAN: CPU Access to the eCAN Registers may Fail if it is in Conflict With an eCAN Access to the eCAN Registers Y Y Y Y Y Y Y Y
eCAN: Unexpected Cessation of Transmit Operation Y Y Y Y Y Y Y Y
WD: WDFLAG Bit Does Not Work as Intended Y Y Y Y Y Y Y Y
WD: A Low Output on GPIOF14 Can Disable the PLL and Watchdog if the Watchdog Fires a Reset Y Y N/A N/A N/A N/A N/A N/A
ADC: EOS BUF1/2 Bits in ADCST Corrupted at the End of Conversion of Sequencer 1/2 When INT MOD SEQ1/2 is Enabled Y Y Y Y Y Y Y Y
ADC: Reserved Bits in Autosequence Status Register (ADCASEQSR) Y Y Y Y Y Y Y Y
ADC: Sequencer Reset While Dual Sequencers Are Running Y Y Y Y Y Y Y Y
ADC: Result Register Update Delay Y Y Y Y Y Y Y Y
ADC: Device Has Higher Gain Error Than the Design Goal of 1% FSR on All of the B0−B7 Channels Y Y N/A N/A N/A N/A N/A N/A
ADC: Device Has Higher Offset Error Than the Design Goal (0.5 to 1%) on Some Channels Y Y N/A N/A N/A N/A N/A N/A
ADC: Device Has Higher Non-Linearity Than the Design Goal of 2 LSBs Y Y N/A N/A N/A N/A N/A N/A
McBSP: Receive FIFO Read Conflict Y Y Y Y Y Y Y Y
McBSP: Read Operations Decrement the McBSP FIFO Y Y Y Y Y Y Y Y
SPI: Slave-Mode Operation Y Y Y Y Y Y Y Y
Clocking: Logic-High Level for XCLKIN Pin Y Y Y Y Y Y Y Y
EV: QEP Circuit Y Y Y Y Y Y Y Y
QEP: QEP Inputs in GPIO Asynchronous Mode Y Y Y Y Y Y Y Y
DEVICE-ID: Register of the Silicon Same for Revision C and Revision D N/A N/A N/A N/A Y N/A N/A N/A
PLL: PLL x4 and x8 Multiplier Ratios Y Y N/A N/A N/A N/A N/A N/A
Low-Power Modes − STANDBY Mode Y Y N/A N/A N/A N/A N/A N/A
(1) Y = Yes; N/A = Not Applicable