SPRZ193T January   2003  – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

 

  1.   1
  2. 1Introduction
  3. 2Device and Development Tool Support Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
  6. 5Known Design Exceptions to Functional Specifications
    1.     Advisory
    2.     Advisory
    3.     Advisory
    4.     Advisory
    5.     Advisory
    6.     Advisory
    7.     Advisory
    8.     Advisory
    9.     Advisory
    10.     Advisory
    11.     Advisory
    12.     Advisory
    13.     Advisory
    14.     Advisory
    15.     Advisory
    16.     Advisory
    17.     Advisory
    18.     Advisory
    19.     Advisory
    20.     Advisory
    21.     Advisory
    22.     Advisory
    23.     Advisory
    24.     Advisory
    25.     Advisory
    26.     Advisory
    27.     Advisory
    28.     Advisory
    29.     Advisory
    30.     Advisory
    31.     Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

Advisory

Clocking: Logic-High Level for XCLKIN Pin

Revision(s) Affected

0, A, B, C, D, E, F and G

Details

This advisory is applicable only when an external oscillator is used to clock the device. The X1/XCLKIN pin is referenced to the core power supply (VDD), rather than the 3.3-V I/O supply (VDDIO). Therefore, the logic-high level for the input clock should not exceed VDD. This requirement remains the same for future silicon revisions as well.

Workaround(s)

A clamping diode may be used to clamp a buffered clock signal to ensure that the logic-high level does not exceed VDD (1.8 V or 1.9 V). Otherwise, 1.8-V oscillators may be used.