SPRZ193T January   2003  – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

 

  1.   1
  2. 1Introduction
  3. 2Device and Development Tool Support Nomenclature
  4. 3Device Markings
  5. 4Usage Notes and Known Design Exceptions to Functional Specifications
    1. 4.1 Usage Notes
      1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
  6. 5Known Design Exceptions to Functional Specifications
    1.     Advisory
    2.     Advisory
    3.     Advisory
    4.     Advisory
    5.     Advisory
    6.     Advisory
    7.     Advisory
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    9.     Advisory
    10.     Advisory
    11.     Advisory
    12.     Advisory
    13.     Advisory
    14.     Advisory
    15.     Advisory
    16.     Advisory
    17.     Advisory
    18.     Advisory
    19.     Advisory
    20.     Advisory
    21.     Advisory
    22.     Advisory
    23.     Advisory
    24.     Advisory
    25.     Advisory
    26.     Advisory
    27.     Advisory
    28.     Advisory
    29.     Advisory
    30.     Advisory
    31.     Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

Advisory

ADC: Sequencer Reset While Dual Sequencers Are Running

Revision(s) Affected

0, A, B, C, D, E, F and G

Details

In the TMS320F2812/TMS320F2811/TMS320F2810 on-chip ADC, there are two sequencers for performing ADC conversions; SEQ1 and SEQ2. If one of the sequencers is reset while the other sequencer is running, it will result in the running sequencer never completing its current sequence. The sequencer busy bit (bit 3/bit 2 in ADCST register) for the sequencer will remain active and an “End-of-sequence (EOS)” interrupt for the running sequencer will never be generated. For example, if SEQ1 is reset while SEQ2 is performing a sequence, then SEQ2 will never complete.

Workaround(s)

If dual sequencers are enabled, then the software handling the ADC module should make sure that SEQ1 BSY/ SEQ2 BSY bits are not set before performing a reset of either sequencer.