SPRZ544C March   2023  – October 2025 AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2351
      2.      i2330
      3.      i2372
      4.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2087
      4.      i2097
      5.      i2134
      6.      i2189
      7.      i2196
      8.      i2199
      9.      i2208
      10.      i2249
      11.      i2278
      12.      i2279
      13.      i2310
      14.      i2311
      15.      i2312
      16.      i2366
      17.      i2371
      18.      i2120
      19.      i2137
      20.      i2190
      21.      i2253
      22.      i2373
      23.      i2383
      24.      i2401
      25.      i2407
      26.      i2409
      27.      i2410
      28.      i2376
      29.      i2399
      30.      i2413
      31.      i2414
      32.      i2419
      33.      i2420
      34.      i2421
      35.      i2422
      36.      i2423
      37.      i2431
      38.      i2435
      39.      i2160
      40.      i2436
      41.      i2482
      42.      i2464
      43.      i2487
      44.      i2493
  4.   Trademarks
  5.   Revision History

i2493

MMCSD: HS200 write failures

Details:

The MMC0 interface has the potential for write failures when issuing multiple block writes operating in HS200 mode with excessive IO supply noise.

To minimize IO supply noise follow below best practices and refer to the linked application note:

  • Use wide power planes/pours adjacent to ground layers with a thin dielectric between them.
  • Place power planes/pours and adjacent ground planes as close to the surface of the powered components as possible.
  • Use a wide variety of decoupling capacitor values and place low ESL capacitors as close to the decoupled device as possible.
  • Use one decoupling capacitor per power pin.
  • Use short and wide traces to decoupling capacitors and power/ground vias.
  • Sitara™ Processor Power Distribution Networks: Implementation and Analysis

Workaround(s):

Implement a software recovery mechanism that re-issues the failed multiple block write with minimum 5μs delay between blocks to reduce noise. One way to achieve this delay is using single block writes for the failed multiple block write.