SPRZ544C March   2023  – October 2025 AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2351
      2.      i2330
      3.      i2372
      4.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2087
      4.      i2097
      5.      i2134
      6.      i2189
      7.      i2196
      8.      i2199
      9.      i2208
      10.      i2249
      11.      i2278
      12.      i2279
      13.      i2310
      14.      i2311
      15.      i2312
      16.      i2366
      17.      i2371
      18.      i2120
      19.      i2137
      20.      i2190
      21.      i2253
      22.      i2373
      23.      i2383
      24.      i2401
      25.      i2407
      26.      i2409
      27.      i2410
      28.      i2376
      29.      i2399
      30.      i2413
      31.      i2414
      32.      i2419
      33.      i2420
      34.      i2421
      35.      i2422
      36.      i2423
      37.      i2431
      38.      i2435
      39.      i2160
      40.      i2436
      41.      i2482
      42.      i2464
      43.      i2487
      44.      i2493
  4.   Trademarks
  5.   Revision History

i2424

PLL: PLL Programming Sequence May Introduce PLL Instability

Details:

PLL programming sequence has been changed to ensure that, if used, all calibration fields are configured prior to enabling the PLL calibration. In addition to the change to the control of the calibration logic, other changes are implemented so that PLL parameters are unchanged while the PLL is enabled.

When in integer mode, the software enables the PLL calibration feature on calibration-capable PLLs. The previous software adjusted calibration modes after CAL_LOCK was asserted. These writes have been observed to cause a loss of PLL lock on some devices. Additionally, even on susceptible devices, the loss of lock is intermittent, but when the loss occurs, dependent circuitry runs at an incorrect frequency; this wrong frequency can show up as slow algorithm execution or communication failures.

Limit on the impact: The calibration logic cannot be used when the PLL is in fractional mode. Therefore, PLLs that are programmed to use fractional mode should not see a failure related to the calibration programmation. Nevertheless, because of the change to the full PLL sequence, the new software is recommended for all users.

Workaround(s):

Do not use clk_pll_16fft_cal_option4() in SYSFW. Ensure to use updated PLL programming sequences in SDK v10.0 or later when performing any PLL configuration change.