SPVA024 June   2025 ADC810-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  POR
    6. 5.6  Timing Characteristics
    7. 5.7  Analog/Digital IO
      1. 5.7.1  Electrical Characteristics
      2. 5.7.2 Switching Characteristics
    8. 5.8  ADC
      1. 5.8.1 Electrical Characteristics
      2. 5.8.2 Linearity Parameters
      3. 5.8.3 Switching Characteristics
    9. 5.9  VREF
      1. 5.9.1 Electrical Characteristics
      2. 5.9.2 Voltage Characteristics
    10. 5.10 I2C
      1. 5.10.1 I2C Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Multiplexer
      2. 6.3.2 Voltage Reference
      3. 6.3.3 Oscillator
      4. 6.3.4 Output Data Rate and Conversion Time
      5. 6.3.5 Digital Comparator
      6. 6.3.6 Conversion Ready Pin
      7. 6.3.7 Interrupt Output (INT)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset and Power-Up
      2. 6.4.2 Operating Modes
        1. 6.4.2.1 Single-Shot Mode
        2. 6.4.2.2 Continuous-Conversion Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Interface
        1. 6.5.1.1 I2C Address Selection
        2. 6.5.1.2 I2C General Call
        3. 6.5.1.3 I2C Speed Modes
      2. 6.5.2 Target Mode Operations
        1. 6.5.2.1 Receive Mode
        2. 6.5.2.2 Transmit Mode
      3. 6.5.3 Writing To and Reading From the Registers
      4. 6.5.4 Data Format
  8. 7 Register Map
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Schematic
      2. 8.1.2 ADC Configuration Examples
      3. 8.1.3 GPIO Configuration Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.1.1 Schematic

TI recommends connecting a combination of a 10µF and a 0.1µF low-ESR ceramic decoupling capacitor to the VDD and VSS pins. Higher-value capacitors can be used, but they can affect the supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins (within a few millimeters).

Pull-up resistors are required on both the SDA and SCL lines because I2C bus drivers are open-drain. Additionally, pull-up resistors are required on both INT and ALERT/RDY pins because both pins are open-drain.

ADC810 ADC810-Q1 Typical Application SchematicFigure 8-1 Typical Application Schematic.