STDA022 January   2026 MSPM0L1305

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Background
  6. 3Procedure
  7. 4Assessment Methods and Results
    1. 4.1 Initial Data Collection
    2. 4.2 BLR With In Situ Monitoring
    3. 4.3 BLR Without In Situ Monitoring
  8. 5Summary of Results
  9. 6Conclusion
  10. 7Acknowledgements
  11. 8References

2 Background

Compared to standard wire bonded QFN packages, wire bonded chip-on-lead (COL) QFN packages enable pin counts to be supported in smaller package body sizes. A non-conductive die attach is used to isolate the die, which sits directly on the package leads, as shown in Figure 2-1.

XM0L1305SRTRR MSPM0L1305
Figure 2-1 Example of a COL QFN Footprint (Left) and SEM Image of a COL Device Prior to Mold (Right)
XM0L1305SRTRR MSPM0L1305

The die must have adequate support on the leads to prevent failures during the wire bond process. These failures can include:

  • Non-stick on the pad (NSOP), where the wire bond machine stops when the machine detects that the wire has not made correct contact with the bond pad.
  • Malformed ball, where the ball bond is not well-formed.
  • Low mean time between assists (MTBA), where the wire bond machine must be restarted frequently.

Thus, a minimum die size is necessary to wire bond based on the specific exposed lead dimensions and layout of a given COL QFN. However, as die shrink with improved silicon capability, the challenge of keeping the same package designator (needed for customer continuity) has increased.

To support smaller die in COL QFN packages, one option is to modify the lead frame and extend the exposed metal of the leads visible on the exterior of the package. This adjustment reduces the distance between leads, meaning, a smaller die can be supported between the leads. However, the implications of this type of change to the package footprint on SMT (when a customer solders the package to their PCB) has not been previously evaluated.

Unless new boards are designed, the extended leads overhang an existing PCB land pad to some extent, as visualized in Figure 2-2. However, a new PCB design is time-consuming and expensive, so reusing an existing PCB and stencil without concern for impacts to SMT (for example, solder joint abnormalities or solder volume thickness) is desirable for customers. Temperature cycle board-level reliability (BLR) testing was chosen as the assessment method to evaluate the effects on solder joint reliability and fatigue when the leads are extended and soldered without changing the PCB.

XM0L1305SRTRR MSPM0L1305 Concept of Lead Overhang Figure 2-2 Concept of Lead Overhang

In terms of the amount of overhang that is permissible, a maximum of 25% of side overhang is recommended (along the lead width) for robustness, but makes no comment regarding overhang along the lead length; the only guidance comes from IPC-A-610 [1].