2 PHY Data Rate Selection and Radar Processing

Radar data processing is generally split into the signal processing and detection stage. The point at which each stage performs determines the Ethernet bandwidth the system requires.

The signal processing stage consists of performing various FFTs on the raw radar data to recover a list of objects with range, velocity, and angle (imaging radars can also have an additional elevation measurement). Each of these FFT steps result in a reduction of the sensor data sent back to ADAS compute. For example, after the range FFT, bins that do not contain targets can be discarded, reducing the amount of data that must be processed further.

The detection stage compresses the stream further by generating a concise object list (ID, range, velocity, angle, and so forth), which transmits to the central compute.

If all processing is performed on the radar SoC (edge), only the compact object list leaves the sensor, and the required link speed is on the order of a few Mbps. When processing is split, the edge can stop after the early FFTs and stream the intermediate data to a central ADAS ECU; in this case, the link must support tens to hundreds of Mbps. Finally, if the central computer is responsible for all processing, the radar must transmit raw samples streamed at several Gbps.

Implications for PHY choice:

• 10BASE-T1s (10Mbps) – Radar SoC performs all radar processing on the edge.
  • Use DP83TD555 or DP83TD535
• 100BASE-T1 (100Mbps) – Radar SoC performs some edge processing; intermediate spectrum data is sent to central compute for additional processing and higher-level fusion.
  • Use DP83TC815 or DP83TC817
• 1000BASE-T1 (1Gbps) – Radar SoC performs only early-stage processing. The bulk of the data streams to the central compute for further FFTs, detection, and sensor-fusion algorithms.
  • Use DP83TG721

TI Ethernet PHYs are available in all three speed classes. System designers can select the PHY to match the selected split-processing architecture.