SWRA370A September   2011  – December 2025 CC1100 , CC1101 , CC2500 , CC2510 , CC2520 , CC2530 , CC2530-RF4CE , CC2540 , CC2540T , CC2541 , CC2541-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Acronyms
  5. 2Standards and System Requirements
    1. 2.1 Standards
    2. 2.2 Test Equipment Suppliers
    3. 2.3 Radio Certification URLs
  6. 3Test Equipment Requirements
    1. 3.1 System Setup
      1. 3.1.1 Conducted Test Systems
      2. 3.1.2 Radiated Test Systems
    2. 3.2 Initial Considerations for Testing
    3. 3.3 Testing Reminders
  7. 4Software Setup
    1. 4.1 SmartRF Studio 7
      1. 4.1.1 SmartRF Studio 7 Start-Up Window
      2. 4.1.2 SmartRF Studio 7 Modes
      3. 4.1.3 SmartRF Studio 7 Device Control Panel
      4. 4.1.4 SmartRF Studio 7 Software User Manual
    2. 4.2 SmartRF Studio 8
      1. 4.2.1 SmartRF Studio 8 Start-Up Window
      2. 4.2.2 SmartRF Studio 8 Radio Control Window
      3. 4.2.3 SmartRF Studio 8 Software User Guide
  8. 5DUT and Test Instrument Information
    1. 5.1 DUT
    2. 5.2 Test Instruments
  9. 6Clock Frequency Tuning
    1. 6.1 HF Clock Tuning Utilizing the Internal Cap Array
    2. 6.2 LF Clock Tuning
  10. 7Transmission Tests
    1. 7.1 Transmission Power
    2. 7.2 Power Spectral Density Mask
    3. 7.3 Error Vector Magnitude
    4. 7.4 Transmission Center Frequency Offset
    5. 7.5 Spurious Emissions
  11. 8Receive Testing
    1. 8.1 Receiver Sensitivity
    2. 8.2 Interference Testing
    3. 8.3 Interference Testing with RF Generator
  12.   Appendix A Offset EVM vs. EVM
  13.   B References
  14.   B Revision History

6.2 LF Clock Tuning

Purpose: To adjust the LF crystal's load capacitance to tune the LF crystal clock accuracy to meet the crystal clock accuracy spec.

Pass Condition: The LF clock output frequency is within crystal data sheet specified tolerances with the final load capacitor values installed.

Low Frequency Clock Tuning Bench Setup Figure 6-3 Low Frequency Clock Tuning Bench Setup

Procedure:

  • Step 1: Generate a software load using Code Composer that outputs the LF clock to a GPIO that can easily be probed.
  • Step 2: Using your preferred programming tool (Uniflash or SmartRF Flash Programmer), program the device with the software load.
  • Step 3: Connect the instruments as shown on Figure 6-3.
  • Step 4: Power up the device and measure the frequency of the GPIO pin assigned to output the LF clock.
  • Step 5: If the LF clock frequency is out of tolerance or is not as close to the rated frequency as desired, adjust the load capacitance to shift the frequency appropriately. In general, increasing load capacitance reduces the frequency and reducing load capacitance increases the frequency.
  • Step 6: Once the load capacitance is adjusted, repeat Steps 4 and 5 until the desired frequency clock accuracy is achieved.
Table 6-3 LF Oscillator Results
Capacitor 1 Value Capacitor 2 Value Output Frequency PPM
1
2
3