SWRU629A September   2024  – February 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Wired Connections, Jumper Settings, Buttons, and LEDs
      1. 2.1.1  SWD Interface
      2. 2.1.2  I2C Connections
        1. 2.1.2.1 Default I2C Addresses
      3. 2.1.3  UART Signals
      4. 2.1.4  SD Card Interface
      5. 2.1.5  External Memory Interface
      6. 2.1.6  ADC Interface
      7. 2.1.7  Reset Pullup Jumper
      8. 2.1.8  Push Buttons
      9. 2.1.9  LED Indicators
      10. 2.1.10 LaunchPad Header Pin Assignment
    2. 2.2 Power
      1. 2.2.1 VIO Selection
      2. 2.2.2 Measure the CC35xxE Current Draw
        1. 2.2.2.1 Low Current Measurement (LPDS)
        2. 2.2.2.2 Active Current Measurement
    3. 2.3 Clocking
    4. 2.4 Conducted RF Testing
    5. 2.5 Evaluation Setup
      1. 2.5.1 Wi-Fi Toolbox LP-EM-CC35X1 Hardware Setup
  7. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  8. 4Additional Information
    1. 4.1 Trademarks
  9. 5Revision History

VIO Selection

The CC35xxE device features three Voltage IO rings (VIOs) for choosing the reference voltage of the various IOs. These three VIOs are VIO1, VIO2, and VDDSF. Each one of the IO rings can be set to 1.8V or 3.3V independently of each other.

The LP-EM-CC35X1 features 2 jumpers (J10, J11) for easy voltage configuration for VIO1 and VIO2, either to 1.8V or 3.3V. By default both are set to 3.3V; see Figure 2-18.

LP-EM-CC35X1 VIO JumpersFigure 2-18 VIO Jumpers

To set either VIO to 1.8V instead of 3.3V, place the jumper on the left two header pins. For example, VIO1 is set to 1.8V and VIO2 is set to 3.3V as shown in Figure 2-19.

LP-EM-CC35X1 VIO Selection ExampleFigure 2-19 VIO Selection Example

VDDSF IO ring controls the reference voltage of the xSPI signals to the external flash. For more information on VDDSF, see Section 2.1.5.

For the VIO selection of each GPIO, see Table 2-8.

Table 2-8 GPIO VIO Selection
LaunchPad Header Pin #Default Setting on LP-EM-CC35X1 CC35xx GPIO #IO Ring
13.3VN/AN/A
2SLOW_CLK_INGPIO0VIO1
3UART0 RXGPIO18VIO1
4UART0 TXGPIO17VIO1
5I2C1 DataGPIO10VIO1
6I2C1 CLKGPIO11VIO1
7SPI0 CLKGPIO27VIO2
8SPI1 CLKGPIO14VIO1
9I2C0 CLK, PDM Data0GPIO33VIO2
10I2C0 Data, PDM BCLKGPIO32VIO2
11SPI1 POCIGPIO15VIO1
12SPI1 CSGPIO12VIO1
13SPI1 PICOGPIO13VIO1
14SPI0 POCIGPIO28VIO2
15SPI0 PICOGPIO29VIO2
16ResetN/AN/A
17GPT1_1GPIO30VIO2
18SPI0 CSGPIO26VIO2
19GPT1_3GPIO2VIO1
20GNDN/AN/A
215VN/AN/A
22GNDN/AN/A
23ADC2GPIO6VIO1
24ADC3GPIO5VIO1
25ADC4GPIO4VIO1
26ADC5GPIO3VIO1
27I2S WCLKGPIO26VIO2
28I2S MCLK/BCLKGPIO29VIO2
29I2S Data0GPIO30VIO2
30I2S Data1GPIO31, GPIO35VIO2
31DCAN RXGPIO34VIO2
32DCAN TXGPIO30VIO2
33GPT0_1GPIO35VIO2
34LoggerN/AN/A
35UART1 RXGPIO6VIO1
36UART1 TXGPIO5VIO1
37UART0 RTSGPIO16VIO1
38UART0 CTSGPIO19VIO1
39GPIOGPIO4VIO1
40N/AGPIO36VIO1