SWRU639 February   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Block Diagram
      1. 2.1.1 Design Considerations
    2. 2.2 Power Requirements
      1. 2.2.1 System Design Theory
    3. 2.3 Highlighted Products
      1. 2.3.1 AWR2243
      2. 2.3.2 AM2732R
      3. 2.3.3 LP876242-Q1
      4. 2.3.4 LM62460-Q1
      5. 2.3.5 TCAN1043A-Q1
      6. 2.3.6 TCAN1044A-Q1
      7. 2.3.7 TMP102-Q1
      8. 2.3.8 TPS61379-Q1
      9. 2.3.9 DP83TC812-Q1
    4. 2.4 Virtual Antenna Array
  9. 3Implementation Results
    1. 3.1 Performance Data and Results
      1. 3.1.1 Angle Resolution Measurement
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout Recommendations
      1. 4.2.1 20GHz (FMCW) RF LO Sync
      2. 4.2.2 PCB Layer Stackup
    3. 4.3 BOM
  11. 5Tools and Software
  12. 6Related Documentation
    1.     Supplemental Content
  13. 7Additional Information
    1. 7.1 Trademarks
  14. 8Revision History

2.2.1 System Design Theory

For systems with additional safety requirements, diagnostic and monitoring features have been included in this reference design.

  • Voltage Monitors (VMON): The voltage monitoring pins within the LP876242-Q1 have been connected to the 1V2_FILTERED and 5V rails. In the event of an under voltage or over voltage event, this allows the PMIC to monitor these rails and using SOC_nRESET_FROM_PMIC (GPIO10) issue a hard reset to the SOC. These inputs are low pass filtered to eliminate any short term events that would not adversely affect the operation of the system. The connection of these monitors is made directly at the connection to the radar. This avoids the situation where the ferrite bead in the power filters could fail and not be detected. The VMON thresholds and the actions taken during an OV/UV condition are configured in the Non-Volatile Memory (NVM) settings of the PMIC, and are re-configurable over SPI.
  • Additional Voltage Monitoring: To monitor the VIN_RF1 and VIN_RF2 rails, they are connected to ADC inputs on the SOC. If the rails monitored by the PMIC are functioning correctly, the SOC will be powered and the ADC will be able to monitor the RF rails. The action(s) taken by the SOC during a failure are configurable in software.