TIDT244 July   2021

 

  1. 1Description
  2. 2Test Prerequisites
    1. 2.1 Voltage and Current Requirements
    2. 2.2 Required Equipment
  3. 3Testing and Results
    1. 3.1 Thermal Images
    2. 3.2 Efficiency and Power Dissipation Graph
    3. 3.3 Efficiency and Power Dissipation Data
    4. 3.4 Current Regulation
    5. 3.5 Voltage Regulation
  4. 4Waveforms
    1. 4.1 Start-up
    2. 4.2 Switch Node
    3. 4.3 Output Voltage Ripple
    4. 4.4 Current Loop to Voltage Loop Transition
    5. 4.5 Voltage Loop to Current Loop Transition
    6. 4.6 Bias Voltage Start-up
    7. 4.7 Bias Voltage Switch Nodes
    8. 4.8 Output Current Sense Signal

4.2 Switch Node

The following figures show the FET switch node voltage (YELLOW) at TP7 under various input and output conditions.

GUID-20210611-CA0I-CKNW-B0FS-FNWQRQ1LB9JS-low.pngFigure 4-3 VIN = 420 V and VOUT = 350 V at 2 A.
Resistive Load (VOUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)
GUID-20210611-CA0I-KN6H-ZVNX-DV53VZ0QJ2NR-low.pngFigure 4-4 VIN = 420 V and VOUT = 400 V at 2 A.
Resistive Load (VOUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)
GUID-20210611-CA0I-KN69-DMQK-V7J3CKJH9VSG-low.pngFigure 4-5 VIN = 400 V and VOUT = 400 V at 2 A.
Resistive Load (VOUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)
GUID-20210616-CA0I-SMLS-LJKC-7ZCVQJQMD08V-low.pngFigure 4-6 VIN = 400 V and VOUT = 400 V at 70 mA.
Resistive Load (VOUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)
GUID-20210611-CA0I-N1N0-R8LP-TJZWPJGKVSPG-low.pngFigure 4-7 VIN = 340 V and VOUT = 400 V at 2 A.
Resistive Load (VOUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)

The following figure shows the FET switch node rise time of 22.8 ns at TP7.

GUID-20210611-CA0I-ZZHC-HHGK-CJG6JXP05NNJ-low.pngFigure 4-8 VIN = 400 V and VOUT = 400 V at 2 A.
Resistive Load (VOUT: 250 V/DIV, 40 ns/DIV, BWL = 800 MHz)