TIDUE73B April   2018  – February 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000™ Real-Time MCU LaunchPad™ Development Kit
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 BiSS-C Protocol
        1. 2.3.1.1 Line Delay Compensation
        2. 2.3.1.2 Processing Time Request by Encoder
        3. 2.3.1.3 Control Communication
      2. 2.3.2 C2000 BiSS-C Encoder Interface Overview
      3. 2.3.3 TIDM-1010 Board Implementation
      4. 2.3.4 MCU Resource Requirements
        1. 2.3.4.1 Input, Output Signals, and CLB Tiles
      5. 2.3.5 CLB BiSS-C Implementation Details
        1. 2.3.5.1 Transaction Waveforms
        2. 2.3.5.2 FRAME_STATE Generation
        3. 2.3.5.3 CLB_SPI_CLOCK Generation
        4. 2.3.5.4 ENCODER_CLOCK (MA) Generation
      6. 2.3.6 PM BiSS-C Interface Library
        1. 2.3.6.1 PM BiSS-C Library Functions
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1010 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Example Code
      4. 3.3.4 Encoder Test
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Software Files
  12. 6Related Documentation
    1.     Trademarks
  13. 7Terminology
  14. 8About the Authors
  15. 9Revision History

2.3.5.3 CLB_SPI_CLOCK Generation

The CLB is responsible for detecting the response of the encoder and then clocking the SPI to receive the data. First consider the duty and frequency of the clock. Figure 2-15 shows the CLB logic which generates the SPI clock. Figure 2-16 shows the corresponding simulation waveform.

The first step is to generate a clock (called SPI_CLOCK) with the specified frequency and duty. In the generation of SPI_CLOCK on the CLK_GEN_TILE:

  • COUNTER_1: Is responsible for the duty and frequency (width) of the clock. The time between the high transition and the low transition of the SPI_CLOCK is measured in the number of CLB clocks. The following match signals are used:
    • zero match: corresponds to the low transition of the clock
    • match1: corresponds to the high transition of the clock
    • match2: corresponds to the width of the clock
  • FSM_1: Generates the clock edges based on the COUNTER_1 match values: match1 and zero match
  • LUT_0: Resets the counter when the clock width is reached as indicated by the COUNTER_1 match2 output

The second step is to align the clock with the received data. This is required for the SPI to receive the response of the encoder correctly. There are two challenges to aligning the clock:

  1. The response can arrive at any time due to cable propagation delay as described in Section 2.3.1.1.
  2. The encoder can also delay the acknowledgment, ACK, to request additional processing time as described in Section 2.3.1.2.

To align the clock, LUT_0 monitors the RESPONSE signal for a rising edge. The first rising edge corresponds to the START bit after the acknowledge (ACK) bit. When this edge is detected, LUT_0 resets COUNTER_1 which aligns the SPI_CLOCK to the response.

The third step is to generate the CLB_SPI_CLOCK based on the internal SPI_CLOCK. As shown in Figure 2-16:

  • SPI_CLOCK is generated for a longer duration then required for the SPI to receive the response
  • CLB_SPI_CLOCK only outputs the number of clocks required to receive the response

This is achieved by using FSM_2 on the FSM_GEN_TILE to generate a SPI_CLOCK_OUTPUT_ENABLE signal. This signal is used by the OUTLUT to allow or block the SPI_CLOCK as required.

TIDM-1010 CLB_SPI_CLOCK GenerationFigure 2-15 CLB_SPI_CLOCK Generation
TIDM-1010 SPI Clock Generation Simulation Waveform
Note: The tile instance TILE4 corresponds to the FSM_GEN_TILE. The tile instance TILE3 corresponds to the CLK_GEN_TILE. Tile usage can vary between designs. See Section 2.3.4.1 for device-specific tile usage.
Figure 2-16 SPI Clock Generation Simulation Waveform