TIDUE73B April   2018  – February 2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 C2000™ Real-Time MCU LaunchPad™ Development Kit
      2. 2.2.2 SN65HVD78
      3. 2.2.3 TLV702
      4. 2.2.4 TPS22918-Q1
    3. 2.3 Design Considerations
      1. 2.3.1 BiSS-C Protocol
        1. 2.3.1.1 Line Delay Compensation
        2. 2.3.1.2 Processing Time Request by Encoder
        3. 2.3.1.3 Control Communication
      2. 2.3.2 C2000 BiSS-C Encoder Interface Overview
      3. 2.3.3 TIDM-1010 Board Implementation
      4. 2.3.4 MCU Resource Requirements
        1. 2.3.4.1 Input, Output Signals, and CLB Tiles
      5. 2.3.5 CLB BiSS-C Implementation Details
        1. 2.3.5.1 Transaction Waveforms
        2. 2.3.5.2 FRAME_STATE Generation
        3. 2.3.5.3 CLB_SPI_CLOCK Generation
        4. 2.3.5.4 ENCODER_CLOCK (MA) Generation
      6. 2.3.6 PM BiSS-C Interface Library
        1. 2.3.6.1 PM BiSS-C Library Functions
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware
      1. 3.1.1 TIDM-1010 Jumper Configuration
    2. 3.2 Software
      1. 3.2.1 C2000 Driver Library (DriverLib)
      2. 3.2.2 C2000 SysConfig
      3. 3.2.3 C2000 Configurable Logic Block Tool
      4. 3.2.4 Installing Code Composer Studio™ and C2000WARE-MOTORCONTROL-SDK
      5. 3.2.5 Locating the Reference Software
    3. 3.3 Testing and Results
      1. 3.3.1 Hardware Configuration
      2. 3.3.2 Building and Loading Project
      3. 3.3.3 Running Example Code
      4. 3.3.4 Encoder Test
      5. 3.3.5 Benchmarks
      6. 3.3.6 Troubleshooting
  10. 4Design Files
  11. 5Software Files
  12. 6Related Documentation
    1.     Trademarks
  13. 7Terminology
  14. 8About the Authors
  15. 9Revision History

2.3.5.4 ENCODER_CLOCK (MA) Generation

The ENCODER_CLOCK, or BiSS MA generation is similar to the CLB_SPI_CLOCK generation shown in the previous section. There are two key differences:

  • The total number of MA clocks generated depend on when the response is received.
  • The end of the MA signal must be held high or low to indicate the CDM bit.

The marker (1) in Figure 2-19 indicates the point when the ACK of the encoder is detected by the logic shown in Figure 2-18. Prior to marker (1) an unknown number of MA clocks are generated. From marker (1) forward, the number of additional MA clocks required is X + 4 + 6 where:

  • X bits: total POSITION bits (Single Turn + Multi Turn)
  • 4 bits: START bit + CDM bit + ERROR bit + WARNING bit
  • 6 bits: CRC bits

This number is stored by the application in the FSM_GEN_TILE HLC register R0. HLC adjusts t the total number of clocks (COUNTER_1 match1) using this value along with the current counter value. For example, see Figure 2-19):

  1. If X = 13, then the application stores 23 in HLC R0
  2. When ACK is detected at marker (1), the HLC program is triggered.
  3. HLC reads the current CLB_ENCODER_CLOCK_COUNT (4) and adds R0 (23) = 27
  4. HLC loads 27 into COUNT_1 match1
  5. When the CLB_ENCODER_CLOCK_COUNT reaches match1, the generation of MA clocks is complete.
TIDM-1010 ENCODER_CLOCK (MA) GenerationFigure 2-17 ENCODER_CLOCK (MA) Generation
TIDM-1010 Encoder ACK Detection LogicFigure 2-18 Encoder ACK Detection Logic
TIDM-1010 MA Generation Simulation Waveform: CDM Signal High
Note: The tile instance TILE4 corresponds to the FSM_GEN_TILE. The tile instance TILE3 corresponds to the CLK_GEN_TILE. Tile usage can vary between designs. See Section 2.3.4.1 for device-specific tile usage.
Figure 2-19 MA Generation Simulation Waveform: CDM Signal High

The CDM bit is one-bit of control data transferred to the encoder each BiSS-C frame. The end of the MA signal must be held high or low to indicate the current CDM bit. Figure 2-19 shows a simulation waveform when the level of BISSC_CDM_BIT is high. Figure 2-20 shows a simulation waveform for BISSC_CDM_BIT signal low. The BISS_CDM_BIT signal is controlled by the C28x CPU writing to GPREG on the tile.

Note: For this discussion, the state of the signal, high or low, refers to the level of the BISS_CDM_BIT signal. The actual CDM bit value is interpreted by the encoder as the inverse of signal level. For example, if the BISS_CDM_BIT signal is high, the encoder detects the CDM bit value as 0. The software library accounts for this inversion.

The FSM_0 of FSM_GEN_TILE appends the BISS_CDM_BIT level to the MA signal when FRAME_STATE changes due to CLB_ENCODER_CLOCK_COMPLETE (Figure 2-17). In the case where the level of BISSC_CDM_BIT is low, an extra edge is removed from ENC_CLOCK_MA by the output (Figure 2-20)

TIDM-1010 MA Generation Simulation Waveform: CDM Signal Low
Note: The tile instance TILE4 corresponds to the FSM_GEN_TILE. The tile instance TILE3 corresponds to the CLK_GEN_TILE. Tile usage can vary between designs. See Section 2.3.4.1 for device-specific tile usage.
Figure 2-20 MA Generation Simulation Waveform: CDM Signal Low