TIDUEZ9B July   2022  – April 2023

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Isolated Current Measurement
    2. 1.2 Band-Pass Filter
    3. 1.3 Analog-to-Digital Conversion
    4. 1.4 Arc Detection Algorithm
    5. 1.5 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Current Transformer Circuit
      2. 2.2.2 Analog Band-Pass Filter
      3. 2.2.3 Analog-to-Digital Conversion
      4. 2.2.4 Power Supply
      5. 2.2.5 Debugging and Status Indication Options
    3. 2.3 Highlighted Products
      1. 2.3.1 TPS259474
      2. 2.3.2 TPS562202
      3. 2.3.3 TPS745
      4. 2.3.4 OPAx322
      5. 2.3.5 ADS8363
      6. 2.3.6 REF5025
      7. 2.3.7 TMDSCNCD280049C
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware and Software Requirements
      1. 3.1.1 Hardware
      2. 3.1.2 Software
        1. 3.1.2.1 Arc Detection Theory
        2. 3.1.2.2 Software Implementation
    2. 3.2 Test Setup
      1. 3.2.1 ControlCARD Configuration
      2. 3.2.2 Setup for Hardware and Software Validation
      3. 3.2.3 Setup for Arc Testing
    3. 3.3 Test Results
      1. 3.3.1 Test Results of Hardware and Software Validation
      2. 3.3.2 Testing With Arcs
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Support Resources
    4. 4.4 Trademarks
  10. 5About the Author
  11. 6Revision History

2.2.3 Analog-to-Digital Conversion

As a next step, the filtered signal is converted to the digital domain. This is done either by the external ADC ADS8363 or by an internal ADC of the C2000 MCU. In case of the ADS8363, only four of the eight channels are used. The outputs of the filters are connected to channel CHA0, CHA1, CHB0, and CHB1 with an additional anti-aliasing filter. The unused inputs are tied to ground. CMA and CMB are the common-mode inputs for channel A and B and are connected to the 2.5-V reference voltage provided by the REF5025, which is also used as reference for the ADC and for biasing the signal after the CT. The SPI of the ADS8363 allows for two data lines, which is necessary to achieve the required data rate if more than two channels of arc detection are implemented. A guide on how the ADS8363 SPI with two data lines is implemented is found in the Interfacing to the ADS8363 Pseudo-Differential Operating Mode application note.

GUID-20220711-SS0I-W9WK-SHTW-BK097LZM5PQR-low.svg Figure 2-5 Schematic Analog-to-Digital Conversion With ADS8363

The required data rate in this design is calculated with Equation 3.

Equation 3. B i t r a t e m i n =   N u m b e r   o f   C h a n n e l s   ×   f s   ×   B i t s   p e r   S a m p l e

where

  • fs = sampling rate

With a sampling rate of 250 kSPS, a maximum number of 4 channels and a 22 bits per sample as shown in the previously-mentioned application note, a bit rate of 22 MBit/s is the result. Since the maximum SPI clock frequency fSPI of the ADS8363 is 20 MHz, there are both data lines necessary to achieve the required bit rate for four-channel operation. The easiest way to adjust the bit rate and therefore the sampling rate is to do continuous sampling with the ADS8363 and just modify the SPI clock, since this clock is used for conversion and data transmission. The SPI clock frequency is calculated with Equation 4.

Equation 4. f S P I =   B i t r a t e N u m b e r   o f   d a t a   l i n e s

where

  • Number of data lines can be either 1 or 2

With the maximum bit rate of 22 MBit/s and 2 data lines used, a SPI clock frequency fSPI of 11 MHz is the result. As another example if only one channel is used a bit rate of 5.5 MBit/s is required which is then implemented only using one data line and fSPI of 5.5 MHz.

For improving signal quality, series termination is implemented for all SPI signals as well as an AC termination for the clock signal. The chip select signal is pulled low permanently, since a continuous sampling is implemented.

In case the internal ADC of the C2000 is used, the filter output signals are connected to a level-shifting stage, which is implemented by another OPA4322. It simply translates the 5-V level to a 3.3-V level before connecting the signals to the analog inputs on the controlCARD connector.