TIDUF17 November   2022 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TMS320F280039C
      2. 2.3.2 UCC21530-Q1
      3. 2.3.3 OPA607-Q1
      4. 2.3.4 LM25184-Q1
      5. 2.3.5 TCAN1044A-Q1
    4. 2.4 System Design Theory
      1. 2.4.1 Three-Phase PMSM Drive
      2. 2.4.2 Field Oriented Control of PM Synchronous Motor
      3. 2.4.3 Field Weakening (FW) and Maximum Torque Per Ampere (MTPA) Control
      4. 2.4.4 Compressor Drive with Automatic Vibration Compensation
      5. 2.4.5 Hardware Prerequisites for Motor Drive
        1. 2.4.5.1 Motor Current Feedback
          1. 2.4.5.1.1 Current Sensing with Three-Shunt
          2. 2.4.5.1.2 Current Sensing with Single-Shunt
        2. 2.4.5.2 Motor Voltage Feedback
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Hardware Board Overview
      2. 3.1.2 Test Conditions
      3. 3.1.3 Test Equipment Required for Board Validation
    2. 3.2 Test Setup
      1. 3.2.1 Hardware Setup
      2. 3.2.2 Software Setup
        1. 3.2.2.1 Code Composer Studio Project
        2. 3.2.2.2 Software Structure
    3. 3.3 Test Procedure
      1. 3.3.1 Level 1 Incremental Build
        1. 3.3.1.1 Project Setup
        2. 3.3.1.2 Running the Application
      2. 3.3.2 Level 2 Incremental Build
        1. 3.3.2.1 Project Setup
        2. 3.3.2.2 Running the Application
      3. 3.3.3 Level 3 Incremental Build
        1. 3.3.3.1 Project Setup
        2. 3.3.3.2 Running the Application
      4. 3.3.4 Level 4 Incremental Build
        1. 3.3.4.1 Project Setup
        2. 3.3.4.2 Running the Application
        3. 3.3.4.3 Tuning Field Weakening and MTPA Control
        4. 3.3.4.4 Tuning Vibration Compensation
        5. 3.3.4.5 CAN FD Command Interface
    4. 3.4 Test Results
      1. 3.4.1 MCU CPU Load, Memory, and Peripheral Usage
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.3.2 UCC21530-Q1

The UCC21530-Q1 is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current. The gate driver is designed to drive IGBTs, Si MOSFETs, and SiC MOSFETs up to 5-MHz with best-in-class propagation delay and pulse-width distortion.

The input side is isolated from the two output drivers by a 5.7-kVRMS reinforced isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 1850 V.

This driver can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). The EN pin pulled low shuts down both outputs simultaneously and allows for normal operation when left open or pulled high. As a fail-safe measure, primary-side logic failures force both outputs low.