TIDUFD9 August   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Half-Bridge Topology
      2. 2.2.2 Power Dissipation Design Consideration
      3. 2.2.3 HPA Drain Capacitor Bank Design
      4. 2.2.4 Gate and Drain Pulsing Considerations
      5. 2.2.5 Additional Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 AFE20408
      2. 2.3.2 LMG2100R026
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
      1. 3.3.1 Initial Hardware Setup
      2. 3.3.2 Install HPA
    4. 3.4 Test Results
      1. 3.4.1 Bias Up and Down the HPA
      2. 3.4.2 HPA Drain Modulation
      3. 3.4.3 HPA Gate Modulation
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.2.2 Power Dissipation Design Consideration

The power dissipation through the FETs need to be considered to show that the thermals are tolerable for the system when implementing a half-bridge implementation for hard switching to generate the drain pulse. The following formulas and system parameters are useful to consider when calculating power loss going through the half-bridge FETs and comparing between different half-bridge architectures for the system.

Equation 1. Conduction loss formula: I2 × RDS(on) × D
Equation 2. Gate charge loss formula: VIN × QOSS × fSW
Equation 3. Output capacitance losses formula: VIN2 × CLOAD × fSW

where

  • D is duty cycle as a percentage
  • fSW is switching frequency
  • CLOAD is load capacitance
  • I is the output current
  • VIN is the input voltage
  • RDS(on) and QOSS are defined in the half-bridge power stages or MOSFET data sheet

The losses above can be multiplied by the junction-to-board thermal resistance found in the thermal information of the half-bridge power stages or MOSFET data sheet to calculate the temperature rise of the end user's board.