TIDUFD9 August   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Half-Bridge Topology
      2. 2.2.2 Power Dissipation Design Consideration
      3. 2.2.3 HPA Drain Capacitor Bank Design
      4. 2.2.4 Gate and Drain Pulsing Considerations
      5. 2.2.5 Additional Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 AFE20408
      2. 2.3.2 LMG2100R026
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
      1. 3.3.1 Initial Hardware Setup
      2. 3.3.2 Install HPA
    4. 3.4 Test Results
      1. 3.4.1 Bias Up and Down the HPA
      2. 3.4.2 HPA Drain Modulation
      3. 3.4.3 HPA Gate Modulation
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.2.4 Gate and Drain Pulsing Considerations

The AFE20408 has up to eight outputs that can be utilized to set the gate bias of eight HPAs and each one can be pulsed between the desired bias point and the pinch-off voltage. The OUT pins can quickly pulse with fast rise and fall times determined by the difference in capacitance between the DAC setting the high-voltage level and the corresponding OUT (for example, DACA0 corresponds to OUTA0, DACA2 corresponds to OUTA2, and so forth). However, the DACA1, DACB1, DACA3, and DACB3 pins have a slower rise time but maintain a fast fall time when pulsing due to higher impedance switches on these outputs. To quickly pulse eight HPAs, an alternative design consideration is to pulse the half bridge leading into the drain of the HPA and then use the eight outputs of the AFE20408 to bias voltage incrementally throughout the operation of the system.