TIDUFD9 August   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Half-Bridge Topology
      2. 2.2.2 Power Dissipation Design Consideration
      3. 2.2.3 HPA Drain Capacitor Bank Design
      4. 2.2.4 Gate and Drain Pulsing Considerations
      5. 2.2.5 Additional Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 AFE20408
      2. 2.3.2 LMG2100R026
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
      1. 3.3.1 Initial Hardware Setup
      2. 3.3.2 Install HPA
    4. 3.4 Test Results
      1. 3.4.1 Bias Up and Down the HPA
      2. 3.4.2 HPA Drain Modulation
      3. 3.4.3 HPA Gate Modulation
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.2.5 Additional Considerations

This reference design pairs with the Qorvo GaN HPA QPA1014 EVM through the J22 to J29 headers at a recommended operating drain voltage of 28V.


TIDA-010289 TIDA-010289 Board: J22 Through J29 Highlighted

Figure 2-2 TIDA-010289 Board: J22 Through J29 Highlighted

In general, GaN HPA can exceed this voltage up to around 50V and the power rail pin mapping into the HPA EVMs vary between EVMs. To make this reference design compatible with other HPAs, the pin mappings on J22 to J29 need to be assessed with the intended EVM to evaluate to check for differences and make any needed adjustments. The designer also needs to replace the capacitor bank with capacitors that have the appropriate power deratings. See the HPA Drain Capacitor Bank Design section of this design guide to verify the capacitance, impedance, and ESR of the capacitor bank can support the higher power transients. The LMG2100R026 selected is a 93V continuous, 100V pulsed, 53A half-bridge power stage supplying the drain voltage can support GaN HPAs even for higher power levels.

The QPA1014 EVM gate voltage range has an upper limit of 0V. The gate voltage range of the AFE20408 is selected based off the VSS and the VCC pins for the lower and upper voltage limits, respectively. A higher voltage limit of up to 10V can be selected by tying the VCC pins to a 10V rail but this requires rework of the reference design.