TIDUFD9 August   2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Half-Bridge Topology
      2. 2.2.2 Power Dissipation Design Consideration
      3. 2.2.3 HPA Drain Capacitor Bank Design
      4. 2.2.4 Gate and Drain Pulsing Considerations
      5. 2.2.5 Additional Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 AFE20408
      2. 2.3.2 LMG2100R026
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
      1. 3.3.1 Initial Hardware Setup
      2. 3.3.2 Install HPA
    4. 3.4 Test Results
      1. 3.4.1 Bias Up and Down the HPA
      2. 3.4.2 HPA Drain Modulation
      3. 3.4.3 HPA Gate Modulation
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

1 System Description

Defense applications, such as radar, electronic warfare, and seeker front ends, transmit RF signals utilizing high-power amplifiers to amplify the signal with enough power to overcome channel losses in often-contested RF environments. Of particular interest is the GaN HPA which provides higher power density, better linearity at given power levels and better efficiency than traditional laterally diffused metal-oxide-semiconductor (LDMOS) HPAs. HPAs dominate performance of the transmitter front end in linearity and efficiency. HPAs also are costly in terms of power consumption. Appropriately biasing and monitoring the HPA bias point improves efficiency and reduces operating costs. The drain current changes based on factors such as temperature, drain voltage, and gate voltage. The drain or gate bias voltage needs to be varied as the HPA changes in temperature over operational time to maximize output efficiency. Operators monitor HPA drain current and temperature to improve reliability. This monitoring enables adjustments to be made to drain or gate voltage levels. Adjustments compensate for changes in HPA drain current levels. The PA biasing circuit traditionally is designed discretely with some GaN bias modules that can be > 125mm2 for just a single output. In the center of this reference design is Texas Instrument's AFE20408 single chip that can monitor and bias up to eight HPAs with an 80% size reduction in biasing circuitry. The AFE20408 offers a standalone gate biasing design that can be toggled on and off. This can be paired with a half-bridge power stage to provide a two-chip drain pulsing and monitoring system for multiple HPAs.