TIDUFK0 October   2026

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Step-Down Converter Subsystem
      2. 2.2.2 Digital-to-Analog Control Set Path
      3. 2.2.3 High-Precision Measurement Front-End (Feedback Path)
    3. 2.3 Highlighted Products
      1. 2.3.1 TPSM8F7x20
      2. 2.3.2 ADS9308V8I
      3. 2.3.3 TMDSCNCD28P65X
      4. 2.3.4 DAC80504
      5. 2.3.5 REF50
      6. 2.3.6 OPAx990
  8. 3System Design Theory
    1. 3.1 Converter Step Down Range
    2. 3.2 Fault Clamping Protection
    3. 3.3 Current Clamping Behavior
  9. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Software
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Voltage Linearity test
      2. 4.4.2 Voltage Regulation Test
      3. 4.4.3 Current Linearity Test
      4. 4.4.4 Output Voltage Ripple
      5. 4.4.5 Full Load Transient Response
      6. 4.4.6 Sudden Load Switch In with Current Clamping Response
      7. 4.4.7 Full Load Voltage Settling Time
  10. 5Design and Documentation Support
    1. 5.1 Tools and Software
      1. 5.1.1 Tools
      2. 5.1.2 Software
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4.     Trademarks
  11. 6About the Author

2.1 Block Diagram

Figure 2-1 shows the block diagram of the TIDA-011001.

The 12V input bus feeds all four channels of the TPSM8F7620 buck power module. Each channel independently steps down the 12V rail to a regulated output voltage set by the position of its FB pin. The C2000 MCU issues a 16-bit digital code to the DAC80504 over a high-speed SPI bus; the DAC output drives a resistor network at the FB pin of each buck channel, injecting a bias current that shifts the regulated output voltage. On the feedback path, the ADS9308V8I samples each channel's load voltage and high-side shunt current simultaneously, returning the measurements to the C2000 MCU over a second SPI bus. The MCU closes the loop by computing a 2P2Z correction and writing an updated DAC code.

TIDA-011001 System Block DiagramFigure 2-1 System Block Diagram