SNAS674B September   2015  – February 2017 LMK61E2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Supply
    6. 6.6  LVPECL Output Characteristics
    7. 6.7  LVDS Output Characteristics
    8. 6.8  HCSL Output Characteristics
    9. 6.9  OE Input Characteristics
    10. 6.10 ADD Input Characteristics
    11. 6.11 Frequency Tolerance Characteristics
    12. 6.12 Power-On/Reset Characteristics (VDD)
    13. 6.13 I2C-Compatible Interface Characteristics (SDA, SCL)
    14. 6.14 PSRR Characteristics
    15. 6.15 Other Characteristics
    16. 6.16 PLL Clock Output Jitter Characteristics
    17. 6.17 Typical 156.25-MHz Output Phase Noise Characteristics
    18. 6.18 Typical 161.1328125 MHz Output Phase Noise Characteristics
    19. 6.19 Additional Reliability and Qualification
    20. 6.20 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Block-Level Description
      2. 8.3.2  Device Configuration Control
      3. 8.3.3  Register File Reference Convention
      4. 8.3.4  Configuring the PLL
      5. 8.3.5  Integrated Oscillator
      6. 8.3.6  Reference Doubler
      7. 8.3.7  Phase Frequency Detector
      8. 8.3.8  Feedback Divider (N)
      9. 8.3.9  Fractional Circuitry
      10. 8.3.10 Charge Pump
      11. 8.3.11 Loop Filter
      12. 8.3.12 VCO Calibration
      13. 8.3.13 High-Speed Output Divider
      14. 8.3.14 High-Speed Clock Output
      15. 8.3.15 Device Status
        1. 8.3.15.1 Loss of Lock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Interface and Control
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Block Register Write
      3. 8.5.3 Block Register Read
      4. 8.5.4 Write SRAM
      5. 8.5.5 Write EEPROM
      6. 8.5.6 Read SRAM
      7. 8.5.7 Read EEPROM
    6. 8.6 EEPROM Map
    7. 8.7 Register Map
      1. 8.7.1 Register Descriptions
        1. 8.7.1.1  VNDRID_BY1 Register; R0
        2. 8.7.1.2  VNDRID_BY0 Register; R1
        3. 8.7.1.3  PRODID Register; R2
        4. 8.7.1.4  REVID Register; R3
        5. 8.7.1.5  SLAVEADR Register; R8
        6. 8.7.1.6  EEREV Register; R9
        7. 8.7.1.7  DEV_CTL Register; R10
        8. 8.7.1.8  XO_CAPCTRL_BY1 Register; R16
        9. 8.7.1.9  XO_CAPCTRL_BY0 Register; R17
        10. 8.7.1.10 DIFFCTL Register; R21
        11. 8.7.1.11 OUTDIV_BY1 Register; R22
        12. 8.7.1.12 OUTDIV_BY0 Register; R23
        13. 8.7.1.13 PLL_NDIV_BY1 Register; R25
        14. 8.7.1.14 PLL_NDIV_BY0 Register; R26
        15. 8.7.1.15 PLL_FRACNUM_BY2 Register; R27
        16. 8.7.1.16 PLL_FRACNUM_BY1 Register; R28
        17. 8.7.1.17 PLL_FRACNUM_BY0 Register; R29
        18. 8.7.1.18 PLL_FRACDEN_BY2 Register; R30
        19. 8.7.1.19 PLL_FRACDEN_BY1 Register; R31
        20. 8.7.1.20 PLL_FRACDEN_BY0 Register; R32
        21. 8.7.1.21 PLL_MASHCTRL Register; R33
        22. 8.7.1.22 PLL_CTRL0 Register; R34
        23. 8.7.1.23 PLL_CTRL1 Register; R35
        24. 8.7.1.24 PLL_LF_R2 Register; R36
        25. 8.7.1.25 PLL_LF_C1 Register; R37
        26. 8.7.1.26 PLL_LF_R3 Register; R38
        27. 8.7.1.27 PLL_LF_C3 Register; R39
        28. 8.7.1.28 PLL_CALCTRL Register; R42
        29. 8.7.1.29 NVMSCRC Register; R47
        30. 8.7.1.30 NVMCNT Register; R48
        31. 8.7.1.31 NVMCTL Register; R49
        32. 8.7.1.32 MEMADR Register; R51
        33. 8.7.1.33 NVMDAT Register; R52
        34. 8.7.1.34 RAMDAT Register; R53
        35. 8.7.1.35 NVMUNLK Register; R56
        36. 8.7.1.36 INT_LIVE Register; R66
        37. 8.7.1.37 SWRST Register; R72
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Jitter Considerations in Serdes Systems
      2. 9.2.2 Frequency Margining
        1. 9.2.2.1 Fine Frequency Margining
        2. 9.2.2.2 Coarse Frequency Margining
      3. 9.2.3 Design Requirements
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 Custom Design With WEBENCH® Tools
          2. 9.2.3.1.2 Device Selection
          3. 9.2.3.1.3 VCO Frequency Calculation
          4. 9.2.3.1.4 Device Configuration
          5. 9.2.3.1.5 PLL Loop Filter Design
          6. 9.2.3.1.6 Spur Mitigation Techniques
            1. 9.2.3.1.6.1 Phase Detection Spur
            2. 9.2.3.1.6.2 Integer Boundary Fractional Spur
            3. 9.2.3.1.6.3 Primary Fractional Spur
            4. 9.2.3.1.6.4 Sub-Fractional Spur
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ensured Thermal Reliability
      2. 11.1.2 Best Practices for Signal Integrity
      3. 11.1.3 Recommended Solder Reflow Profile
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

1 Features

  • Ultra-Low Noise, High Performance
    • Jitter: 90 fs RMS Typical fOUT > 100 MHz
    • PSRR: –70 dBc, Robust Supply Noise Immunity
  • Flexible Output Format; User Selectable
    • LVPECL up to 1 GHz
    • LVDS up to 900 MHz
    • HCSL up to 400 MHz
  • Total Frequency Tolerance of ±50 ppm
  • System Level Features
    • Frequency Margining: Fine and Coarse
    • Internal EEPROM: User Configurable Default Settings
  • Other Features
    • Device Control: I2C
    • 3.3-V Operating Voltage
    • Industrial Temperature Range (–40ºC to +85ºC)
    • 7-mm × 5-mm 8-Pin Package
    • Create a Custom Design Using the LMK61E2 With the WEBENCH® Power Designer

2 Applications

  • High-Performance Replacement for Crystal-, SAW-, or Silicon-Based Oscillators
  • Switches, Routers, Network Line Cards, Base Band Units (BBU), Servers, Storage/SAN
  • Test and Measurement
  • Medical Imaging
  • FPGA, Processor Attach

3 Description

The LMK61E2 device is an ultra-low jitter PLLatinum™ programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL, LVDS, or HCSL.

The device features self start-up from on-chip EEPROM that is factory programmed to generate 156.25-MHz LVPECL output. The device registers and EEPROM settings are fully programmable in-system through I2C serial interface. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ± 5% supply.

The device provides fine and coarse frequency margining options through I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing.

Device Information(1)

PART NUMBER DEFAULT OUTPUT FREQ (MHz) AND FORMAT PACKAGE AND BODY SIZE (NOM)
LMK61E2 156.25 LVPECL 8-pin QFM (SIA), 7.00 mm x 5.00 mm
LMK61E2BAA 156.25 LVDS
LMK61E2BBA 125 LVDS
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Pinout and Simplified Block Diagram

LMK61E2 pinout_functional_block_diagram_snas674.gif