156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator
Product details
Parameters
Package | Pins | Size
Features
- Ultra-Low Noise, High Performance
- Jitter: 90 fs RMS Typical fOUT > 100 MHz
- PSRR: –70 dBc, Robust Supply Noise Immunity
- Flexible Output Format; User Selectable
- LVPECL up to 1 GHz
- LVDS up to 900 MHz
- HCSL up to 400 MHz
- Total Frequency Tolerance of ±50 ppm
- System Level Features
- Frequency Margining: Fine and Coarse
- Internal EEPROM: User Configurable Default Settings
- Other Features
- Device Control: I2C
- 3.3-V Operating Voltage
- Industrial Temperature Range (–40ºC to +85ºC)
- 7-mm × 5-mm 8-Pin Package
- Create a Custom Design Using the LMK61E2 With the WEBENCH® Power Designer
Description
The LMK61E2 device is an ultra-low jitter PLLatinum programmable oscillator with a fractional-N frequency synthesizer with integrated VCO that generates commonly used reference clocks. The outputs can be configured as LVPECL, LVDS, or HCSL.
The device features self start-up from on-chip EEPROM that is factory programmed to generate 156.25-MHz LVPECL output. The device registers and EEPROM settings are fully programmable in-system through I2C serial interface. Internal power conditioning provide excellent power supply ripple rejection (PSRR), reducing the cost and complexity of the power delivery network. The device operates from a single 3.3-V ± 5% supply.
The device provides fine and coarse frequency margining options through I2C serial interface to support system design verification tests (DVT), such as standard compliance and system timing margin testing.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The LMK05028EVM is an evaluation module for the LMK05028 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
The LMK05028 integrates two Digital PLLs (DPLLs) with programmable bandwidth for input wander and jitter (...)
Features
- Dual DPLLs with programmable bandwidths and Analog PLLs for frequency translation
- 4 clock inputs supporting hitless switching and holdover
- 8 differential or 16 LVCMOS output clocks or combination of both
- On-chip EEPROM for custom start-up clock clocks
- Flexible oscillator options: onboard XOs, TCXO, or (...)
Description
The EVM can be used as a flexible, synchronous clock source for rapid evaluation, compliance testing, and system prototyping. SMA ports provide access to the LMK05318 clock inputs and outputs for (...)
Features
- One Digital PLL (DPLL) with programmable bandwidths and Two Fractional Analog PLLs (APLLs) for Flexible Clock Generation
- Two reference inputs to the DPLL supporting hitless switching & holdover
- Eight output clocks with 50-fs RMS phase jitter (12 kHz to 20 MHz)
- On-chip EEPROM for custom start-up clock (...)
Description
The LMK61E2EVM evaluation modules provides a complete platform to evaluate the 90-fs RMS jitter performance and configurability of the Texas Instruments LMK61E2 Ultra-Low Jitter Programmable Differential Oscillator with integrated EEPROM and frequency margining capabilities.
The LMK61E2EVM can be (...)
Features
- Ultra low jitter differential clock generation
- Powered over USB or externally (SMA connector)
- Onboard USB to I2C interface
- Coarse and Fine Frequency margining
- GUI platform for full access to LMK03328 registers and EEPROM
Software development
Which software do I use?
| Product | Loop (...) |
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Features
- Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
- Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
- Presents clear and intuitive block (...)
Reference designs
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| QFM (SIA) | 8 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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