74ACT11240

ACTIVE

Octal Buffers/Line Drivers With 3-State Outputs

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Product details

Parameters

Technology Family ACT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 8 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 80 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Data rate (Mbps) 180 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other Inverting buffer/driver

Features

  • Inputs Are TTL-Voltage Compatible
  • Flow-Through Architecture Optimizes PCB Layout
  • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT)

 

EPIC is a trademark of Texas Instruments Incorporated.

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Description

This octal buffer or line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device provides inverting outputs and symmetrical active-low output-enable () inputs. This device features high fan-out and improved fan-in.

The 74ACT11240 is characterized for operation from -40°C to 85°C.

 

 

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Octal Buffer/Line Driver With 3-State Outputs datasheet (Rev. A) Apr. 01, 1996
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCAM077.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options

Ordering & quality

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