74ACT16651

ACTIVE

16-Bit Transceivers And Registers With 3-State Outputs

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Product details

Parameters

Technology Family ACT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Bits (#) 16 Voltage (Nom) (V) 5 F @ nom voltage (Max) (MHz) 90 ICC @ nom voltage (Max) (mA) 0.08 Propagation delay (Max) (ns) 11.9 IOL (Max) (mA) 24 IOH (Max) (mA) -24 Operating temperature range (C) -40 to 85 open-in-new Find other Registered transceiver

Package | Pins | Size

SSOP (DL) 56 191 mm² 18.42 x 10.35 open-in-new Find other Registered transceiver

Features

  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • Inverting Data Paths
  • Independent Registers and Enables for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Packaged in Plastic 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

 

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

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Description

The SN54ACT16651 and 74ACT16651 are 16-bit bus transceivers that consist of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. These devices can be used as two 8-bit transceivers or one 16-bit transceiver.

Complementary output-enable (OEAB and ) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN54ACT16651 and 74ACT16651.

 

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and . In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.

The 74ACT16651 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The SN54ACT16651 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16651 is characterized for operation from -40°C to 85°C.

 

 

 
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Technical documentation

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Type Title Date
* Datasheet 16-Bit Transceivers And Registers With 3-State Outputs datasheet (Rev. A) Apr. 01, 1996
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

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SSOP (DL) 56 View options

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