ADC083000

ACTIVE

8-Bit, 3.0-GSPS Analog-to-Digital Converter (ADC)

Top

Product details

Parameters

Sample rate (Max) (MSPS) 3000 Resolution (Bits) 8 Number of input channels 1 Interface type Parallel LVDS Analog input BW (MHz) 3000 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.82 Power consumption (Typ) (mW) 1900 Architecture Folding Interpolating SNR (dB) 45.4 ENOB (Bits) 7.2 SFDR (dB) 57 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

HLQFP (NNB) 128 484 mm² 22 x 22 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR output clocking
  • Serial Interface for Extended Control
  • Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock
  • Test pattern

  • Key Specifications

    Resolution

    8 Bits

    Max Conversion Rate

    3 GSPS (min)

    Error Rate

    10 -18 (typ)

    ENOB @ 748 MHz Input

    7.0 Bits (typ)

    SNR @ 748 MHz

    44.5 dB (typ)

    Full Power Bandwidth

    3 GHz (typ)

  • Power Consumption
  • Operating

    1.9 W (typ)

    Power Down Mode

    25 mW (typ)


    open-in-new Find other High-speed ADCs (>10MSPS)

    Description

    The ADC083000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 3.4 GSPS. Consuming a typical 1.9 Watts at 3 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable an excellent response of all dynamic parameters up to Nyquist, producing a high 7.0 Effective Number Of Bits, (ENOB) with a 748 MHz input signal and a 3 GHz sample rate while providing a 10 -18 Word Error Rate. The ADC083000 achieves a 3 GSPS sampling rate by utilizing both the rising and falling edge of a 1.5 GHz input clock. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.15V.

    The ADC has a 1:4 demultiplexer that feeds four LVDS buses and reduces the output data rate on each bus to a quarter of the sampling rate.

    The converter typically consumes less than 25 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40°C TA +85°C) temperature range.


    open-in-new Find other High-speed ADCs (>10MSPS)
    Download
    Similar products you might be interested in
    open-in-new Compare products
    Similar functionality to the compared device.
    ADC08B3000 ACTIVE 8-Bit, 3.0-GSPS Analog-to-Digital Converter (ADC) with 4K Buffer Same speed and resolution, with internal 4-k data buffer

    Technical documentation

    star = Top documentation for this product selected by TI
    No results found. Please clear your search and try again.
    View all 7
    Type Title Date
    * Data sheet ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter datasheet (Rev. N) Jul. 06, 2009
    Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
    Technical article How to achieve fast frequency hopping Mar. 03, 2019
    Technical article RF sampling: Learning more about latency Feb. 09, 2017
    Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
    User guide Single low power, ultra high speed CMOS A/D Converter User Guide Jan. 27, 2012
    Application note Selecting Amplifiers, ADCs, and Clocks for High-Performance Signal Paths Sep. 13, 2007

    Design & development

    For additional terms or required resources, click any title below to view the detail page where available.

    Design tools & simulation

    SIMULATION MODEL Download
    SNAM005.ZIP (9 KB) - IBIS Model
    SIMULATION TOOL Download
    PSpice® for TI design and simulation tool
    PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
    Features
    • Leverages Cadence PSpice Technology
    • Preinstalled library with a suite of digital models to enable worst-case timing analysis
    • Dynamic updates ensure you have access to most current device models
    • Optimized for simulation speed without loss of accuracy
    • Supports simultaneous analysis of multiple products
    • (...)
    SCHEMATIC Download
    SNAR001.PDF (269 KB)

    CAD/CAE symbols

    Package Pins Download
    HLQFP (NNB) 128 View options

    Ordering & quality

    Information included:
    • RoHS
    • REACH
    • Device marking
    • Lead finish/Ball material
    • MSL rating/Peak reflow
    • MTBF/FIT estimates
    • Material content
    • Qualification summary
    • Ongoing reliability monitoring

    Support & training

    TI E2E™ forums with technical support from TI engineers

    Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

    If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

    Videos