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High-speed ADCs (≥10 MSPS)

ADC08DL500

NOT RECOMMENDED FOR NEW DESIGNS

Dual-Channel, 8-Bit, 500-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADC08DL500

NOT RECOMMENDED FOR NEW DESIGNS
Data sheet Order now

Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 8 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 2000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.84 Power consumption (typ) (mW) 1250 Architecture Folding Interpolating SNR (dB) 46 ENOB (bit) 7.2 SFDR (dB) 55 Operating temperature range (°C) -40 to 70 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 8 Number of input channels 2 Interface type Parallel LVDS Analog input BW (MHz) 2000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.84 Power consumption (typ) (mW) 1250 Architecture Folding Interpolating SNR (dB) 46 ENOB (bit) 7.2 SFDR (dB) 55 Operating temperature range (°C) -40 to 70 Input buffer Yes
LQFP (PGE) 144 484 mm² 22 x 22

  • Single +1.9V ±0.1V Operation
  • Duty Cycle Corrected Sample Clock

    • Key Specifications

    Resolution

    8 Bits

    Max Conversion Rate

    500 MSPS

    Code Error Rate

    10 −18 (typ)

    ENOB @ 125 MHz Input

    7.2 Bits (typ)

    DNL

    ±0.15 LSB (typ)

  • Power Consumption

    • Operating in 1:2 Demux Output

    1.25W (typ)

    Power Down Mode

    3.3 mW (typ)

  • Single +1.9V ±0.1V Operation
  • Duty Cycle Corrected Sample Clock

    • Key Specifications

    Resolution

    8 Bits

    Max Conversion Rate

    500 MSPS

    Code Error Rate

    10 −18 (typ)

    ENOB @ 125 MHz Input

    7.2 Bits (typ)

    DNL

    ±0.15 LSB (typ)

  • Power Consumption

    • Operating in 1:2 Demux Output

    1.25W (typ)

    Power Down Mode

    3.3 mW (typ)

    The ADC08DL500 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL500 digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective Number of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a 10 −18 Code Error Rate (C.E.R.)

    The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 144-lead LQFP and operates over the modified Industrial (-40°C ≤ TA ≤ +70°C) temperature range.

    The ADC08DL500 is a dual, low power, high performance, CMOS analog-to-digital converter. The ADC08DL500 digitizes signals to 8 bits of resolution at sample rates up to 500 MSPS. Consuming a typical 1.2 Watts in demultiplex mode at 500 MSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration schemes enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective Number of Bits (ENOB) with a 125 MHz input signal and a 500 MHz sample rate while providing a 10 −18 Code Error Rate (C.E.R.)

    The converter typically consumes 3.3 mW in the Power Down Mode and is available in a lead-free 144-lead LQFP and operates over the modified Industrial (-40°C ≤ TA ≤ +70°C) temperature range.

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    * Data sheet ADC08DL500 Low Power, 8-Bit, Dual 500 MSPS A/D Converter datasheet (Rev. C) 25 Mar 2011

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