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ADC09DJ800-Q1

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Automotive dual-channel, 9-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface

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Data sheet

ADC09DJ800-Q1

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 800 Resolution (Bits) 9 Number of input channels 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1110 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (Bits) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 125 Input buffer Yes
Sample rate (max) (Msps) 800 Resolution (Bits) 9 Number of input channels 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1110 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (Bits) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 125 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 9 Bit
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications:
    • SNR (–1dBFS, 97MHz): 53.5dBFS
    • ENOB (–1dBFS, 97MHz): 8.51 Bits
    • SFDR (–1dBFS, 97MHz): 64dBFS
    • Noise floor (–20dBFS, 97MHz): –140.5dBFS/Hz
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800MSPS):
    • Quad Channel: 420mW / channel
    • Dual channel: 555mW / channel
    • Single channel: 840mW
  • Power supplies: 1.1V, 1.9V
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 9 Bit
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications:
    • SNR (–1dBFS, 97MHz): 53.5dBFS
    • ENOB (–1dBFS, 97MHz): 8.51 Bits
    • SFDR (–1dBFS, 97MHz): 64dBFS
    • Noise floor (–20dBFS, 97MHz): –140.5dBFS/Hz
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800MSPS):
    • Quad Channel: 420mW / channel
    • Dual channel: 555mW / channel
    • Single channel: 840mW
  • Power supplies: 1.1V, 1.9V

ADC09xJ800-Q1 is a family of quad, dual and single channel, 9-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC09xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC09xJ800-Q1 is a family of quad, dual and single channel, 9-bit, 800MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC09xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
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* Data sheet ADC09xJ800-Q1 Quad, Dual, Single Channel, 800MSPS, 9-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) PDF | HTML 22 Oct 2024

Design & development

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Evaluation board

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User guide: PDF
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Evaluation board

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The TSW12QJ1600 evaluation module (EVM) is designed to evaluate the ADC12QJ1600-Q1 family of high-speed analog-to-digital converters (ADCs) with different front-end options. The EVM is populated with dual ADC12QJ1600-Q1, a 12-bit, quad-channel 1.6GSPS ADC with JESD204B interface and allows for (...)
User guide: PDF
Not available on TI.com
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ADC09xJ800, ADC09xJ1300, ADC12xJ800 and ADC12xJ1600 IBIS-AMI Model (Rev. A)

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