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ADC09SJ800-Q1

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Automotive single-channel, 9-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface

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Data sheet

ADC09SJ800-Q1

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 800 Resolution (Bits) 9 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 830 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (bit) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 125 Input buffer Yes
Sample rate (max) (Msps) 800 Resolution (Bits) 9 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 830 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (bit) 8.5 SFDR (dB) 64 Operating temperature range (°C) -40 to 125 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 9 Bit
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications:
    • SNR (–1 dBFS, 97 MHz): 53.5 dBFS
    • ENOB (–1 dBFS, 97 MHz): 8.51 Bits
    • SFDR (–1 dBFS, 97 MHz): 64 dBFS
    • Noise floor (–20 dBFS, 97 MHz): –140.5 dBFS/Hz
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800 MSPS):
    • Quad Channel: 420 mW / channel
    • Dual channel: 555 mW / channel
    • Single channel: 840 mW
  • Power supplies: 1.1 V, 1.9 V
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 9 Bit
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications:
    • SNR (–1 dBFS, 97 MHz): 53.5 dBFS
    • ENOB (–1 dBFS, 97 MHz): 8.51 Bits
    • SFDR (–1 dBFS, 97 MHz): 64 dBFS
    • Noise floor (–20 dBFS, 97 MHz): –140.5 dBFS/Hz
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800 MSPS):
    • Quad Channel: 420 mW / channel
    • Dual channel: 555 mW / channel
    • Single channel: 840 mW
  • Power supplies: 1.1 V, 1.9 V

ADC09xJ800-Q1 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC09xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4 GHz.

ADC09xJ800-Q1 is a family of quad, dual and single channel, 9-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC09xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4 GHz.
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* Data sheet ADC09xJ800-Q1 Quad, Dual, Single Channel, 800-MSPS, 9-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet PDF | HTML 22 Apr 2020

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