Product details

Sample rate (Max) (MSPS) 200 Resolution (Bits) 10 Number of input channels 2 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 900 Features Low Power Rating Catalog Input range (Vp-p) 1.5 Power consumption (Typ) (mW) 450 Architecture Pipeline SNR (dB) 59.9 ENOB (Bits) 9.65 SFDR (dB) 82 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 200 Resolution (Bits) 10 Number of input channels 2 Interface type Parallel CMOS, Parallel LVDS Analog input BW (MHz) 900 Features Low Power Rating Catalog Input range (Vp-p) 1.5 Power consumption (Typ) (mW) 450 Architecture Pipeline SNR (dB) 59.9 ENOB (Bits) 9.65 SFDR (dB) 82 Operating temperature range (C) -40 to 85 Input buffer No
WQFN (NKA) 60 81 mm² 9 x 9
  • Single 1.8V Power Supply Operation.
  • Power Scaling with Clock Frequency.
  • Internal Sample-and-Hold.
  • Internal or External Reference.
  • Power Down Mode.
  • Offset Binary or 2's Complement Output Data Format.
  • LVDS or CMOS Output Signals.
  • 60-pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)
  • Clock Duty Cycle Stabilizer.
  • IF Sampling Bandwidth > 900MHz.

Key Specifications

  • Resolution 10 Bits
  • Conversion Rate 200 MSPS
  • ENOB 9.6 bits (typ) @Fin=70 MHz
  • SNR 59.9 dBFS (typ) @Fin=70 MHz
  • SINAD 59.9 dBFS (typ) @Fin=70 MHz
  • SFDR 82 dBFS (typ) @Fin=70 MHz
  • LVDS Power 450mW (typ) @Fs=200 MSPS
  • CMOS Power 280mW (typ) @Fs=170 MSPS
  • Operating Temp. Range −40°C to +85°C.

All trademarks are the property of their respective owners.

  • Single 1.8V Power Supply Operation.
  • Power Scaling with Clock Frequency.
  • Internal Sample-and-Hold.
  • Internal or External Reference.
  • Power Down Mode.
  • Offset Binary or 2's Complement Output Data Format.
  • LVDS or CMOS Output Signals.
  • 60-pin WQFN Package, (9x9x0.8mm, 0.5mm Pin-Pitch)
  • Clock Duty Cycle Stabilizer.
  • IF Sampling Bandwidth > 900MHz.

Key Specifications

  • Resolution 10 Bits
  • Conversion Rate 200 MSPS
  • ENOB 9.6 bits (typ) @Fin=70 MHz
  • SNR 59.9 dBFS (typ) @Fin=70 MHz
  • SINAD 59.9 dBFS (typ) @Fin=70 MHz
  • SFDR 82 dBFS (typ) @Fin=70 MHz
  • LVDS Power 450mW (typ) @Fs=200 MSPS
  • CMOS Power 280mW (typ) @Fs=170 MSPS
  • Operating Temp. Range −40°C to +85°C.

All trademarks are the property of their respective owners.

The ADC10DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 10-bit digital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC10DV200 may be operated from a single 1.8V power supply. The ADC10DV200 achieves approximately 9.6 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates.

The ADC10DV200 is a monolithic analog-to-digital converter capable of converting two analog input signals into 10-bit digital words at rates up to 200 Mega Samples Per Second (MSPS). The digital output mode is selectable and can be either differential LVDS or CMOS signals. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC10DV200 may be operated from a single 1.8V power supply. The ADC10DV200 achieves approximately 9.6 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450mW at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates.

Download

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 3
Type Title Date
* Data sheet Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs datasheet (Rev. A) 18 Apr 2013
Application note Drivng HSpeed ADCs w/LMH6521 DVGA for High IF AC-Coupled Apps (Rev. A) 26 Apr 2013
User guide ADC10/11DV200, 10/11-Bit, 200 Msps A/D Converter User Guide 20 Feb 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Application software & framework

WAVEVISION5

Data acquisition and analysis software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins Download
WQFN (NKA) 60 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos