Product details

Sample rate (Max) (MSPS) 1800, 3600 Resolution (Bits) 12 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 4180 Architecture Folding Interpolating SNR (dB) 58.6 ENOB (Bits) 9.4 SFDR (dB) 73 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 1800, 3600 Resolution (Bits) 12 Number of input channels 2, 1 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 4180 Architecture Folding Interpolating SNR (dB) 58.6 ENOB (Bits) 9.4 SFDR (dB) 73 Operating temperature range (C) -40 to 85 Input buffer Yes
BGA (NXA) 292 729 mm² 27 x 27
  • Configurable to Either 3.6 GSPS Interleaved or 1.8 GSPS Dual ADC
  • Pin-Compatible with ADC10D1000/1500 and ADC12D1000/1600
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9-V ± 0.1-V Power Supply
  • Key Specifications
    • Resolution: 12 Bits
    • Interleaved 3.6 GSPS ADC
      • Noise Floor Density –153.5 dBm/Hz (typ)
      • IMD3 –61 dBFS (typ)
      • Noise Power Ratio 48.5 dB (typ)
      • Power 4.4 W (typ)
      • Full Power Bandwidth 1.75 GHz (typ)
    • Dual 1.8 GSPS ADC, Fin = 125MHz
      • ENOB: 9.4 (typ)
      • SNR 58.5 dB (typ)
      • SFDR 73 dBc (typ)
      • Power 4.4 W (typ)
      • Full Power Bandwidth 2.8 GHz (typ)
  • Configurable to Either 3.6 GSPS Interleaved or 1.8 GSPS Dual ADC
  • Pin-Compatible with ADC10D1000/1500 and ADC12D1000/1600
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9-V ± 0.1-V Power Supply
  • Key Specifications
    • Resolution: 12 Bits
    • Interleaved 3.6 GSPS ADC
      • Noise Floor Density –153.5 dBm/Hz (typ)
      • IMD3 –61 dBFS (typ)
      • Noise Power Ratio 48.5 dB (typ)
      • Power 4.4 W (typ)
      • Full Power Bandwidth 1.75 GHz (typ)
    • Dual 1.8 GSPS ADC, Fin = 125MHz
      • ENOB: 9.4 (typ)
      • SNR 58.5 dB (typ)
      • SFDR 73 dBc (typ)
      • Power 4.4 W (typ)
      • Full Power Bandwidth 2.8 GHz (typ)

The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in TI’s Ultra-High-Speed ADC family and builds upon the features, architecture and functionality of the 10-bit GHz family of ADCs.

The ADC12D1800 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage.

The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to +85°C.

To achieve full rated performance for fCLK > 1.6 GHz, write the maximum power settings one time to Register 6h through the serial interface; see Section 5.6.1 for more information.

The 12-bit, 3.6 GSPS ADC12D1800 is the latest advance in TI’s Ultra-High-Speed ADC family and builds upon the features, architecture and functionality of the 10-bit GHz family of ADCs.

The ADC12D1800 provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage.

The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to +85°C.

To achieve full rated performance for fCLK > 1.6 GHz, write the maximum power settings one time to Register 6h through the serial interface; see Section 5.6.1 for more information.

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Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC-LD-BB — ADC low-distortion balun board

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

User guide: PDF
Not available on TI.com
Evaluation board

ADC-WB-BB — ADC wideband balun board

One ADC-WB-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

User guide: PDF
Not available on TI.com
Evaluation board

ABACO-3P-FMC160 — Abaco Systems® analog 1-channel wideband input/output ADC/DAC FPGA mezzanine card

The Abaco FMC160 provides one 12-bit 3.6-GSPS analog-to-digital converter (ADC) and one 14-bit 5.7-GSPS digital-to-analog converter (DAC). The module highlights the Texas Instruments ADC12D1800 two-channel, 12-bit, 1.6-GSPS ADC in a daughtercard with an FPGA mezzanine card (FMC) connector using a (...)

Application software & framework

WAVEVISION5

Data acquisition and analysis software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

Simulation model

ADC12D1000 IBIS Model

SNAM014.ZIP (41 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00113 — Driving GSPS ADCs in Single-Channel or Dual-Channel Mode for High Bandwidth Applications

This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00479 — Optimal Clock Sources for GSPS ADCs Reference Design

The ADC12D1600RFRB reference design provides a platform to demonstrate a high speed digitizer application which incorporates clocking, power management, and signal processing. The reference design utilizes the 1.6 GSPS ADC12D1600RF device, onboard FPGA Xilinx Virtex 4, and high performance clock (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00071 — Schematic and Layout Recommendations for the Giga Sample Per Second (GSPS) ADC

This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference (...)
User guide: PDF
Schematic: PDF
Package Pins Download
BGA (NXA) 292 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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