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ADC12DJ5200SE

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Singled-ended input RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

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Data sheet

ADC12DJ5200SE

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Data sheet Order now

Product details

Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 6300 Features High Performance, Ultra High Speed Rating Catalog Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 53.2 ENOB (bit) 8.4 SFDR (dB) 65 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 6300 Features High Performance, Ultra High Speed Rating Catalog Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 53.2 ENOB (bit) 8.4 SFDR (dB) 65 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Single Ended 50 Ω Inputs:
    • Analog input range (–3 dB): 2 to 6.3 GHz
    • Full-scale input power (4.5 GHz): - 1.25 dBm
    • Flexible V CM: AC coupled with no DC path to GND or supply
  • Performance specifications:
    • Noise floor (2.3 GHz, –20 dBFS, INPUT FS = 1.5 dBm):
      • Dual-channel mode: –149 dBFS/Hz
      • Single-channel mode: –151.5 dBFS/Hz
    • ENOB (dual channel, F IN = 2.3 GHz): 8.5 Bits
  • Noiseless aperture delay (t AD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • 4x, 8x, 16x and 32x complex decimation
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power: +26.25 dBm (+ 27.5 dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4 W
  • Power supplies: 1.1 V, 1.9 V
  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Single Ended 50 Ω Inputs:
    • Analog input range (–3 dB): 2 to 6.3 GHz
    • Full-scale input power (4.5 GHz): - 1.25 dBm
    • Flexible V CM: AC coupled with no DC path to GND or supply
  • Performance specifications:
    • Noise floor (2.3 GHz, –20 dBFS, INPUT FS = 1.5 dBm):
      • Dual-channel mode: –149 dBFS/Hz
      • Single-channel mode: –151.5 dBFS/Hz
    • ENOB (dual channel, F IN = 2.3 GHz): 8.5 Bits
  • Noiseless aperture delay (t AD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • 4x, 8x, 16x and 32x complex decimation
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power: +26.25 dBm (+ 27.5 dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4 W
  • Power supplies: 1.1 V, 1.9 V

The ADC12DJ5200SE is an RF-sampling, giga-sample, analog-to-digital converter (ADC) with integrated input baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. The -3 dB input frequency range of 2 to 6.3 GHz enables direct RF sampling of S-band and C-band for frequency agile systems.

The ADC12DJ5200SE uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.

The ADC12DJ5200SE is an RF-sampling, giga-sample, analog-to-digital converter (ADC) with integrated input baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. The -3 dB input frequency range of 2 to 6.3 GHz enables direct RF sampling of S-band and C-band for frequency agile systems.

The ADC12DJ5200SE uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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* Data sheet ADC12DJ5200SE 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) with Integrated Baluns datasheet (Rev. A) PDF | HTML 08 May 2023
User guide ADCxxDJxx00RF Evaluation Module User's Guide (Rev. B) PDF | HTML 02 Mar 2023

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Evaluation board

ADC12DJ5200SEEVM — ADC12DJ5200SE evaluation module for single-ended input RF-sampling 12-bit ADC

The ADC12DJ5200SE evaluation module (EVM) is a platform used to evaluate the ADC12DJ5200SE analog-to-digital converter (ADC). The ADC12DJ5200SE is a dual-channel, 12-bit ADC capable of operating at sampling rates up to 5.2-Giga-samples per second (GSPS) in dual-channel mode, or 10.4-GSPS in (...)

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Simulation model

ADC12DJ5200SE S-Parameter Model

SLVME17.ZIP (176 KB) - S-Parameter Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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