Product details

Sample rate (max) (Msps) 40 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 250 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 210 Architecture Pipeline SNR (dB) 69 ENOB (bit) 11.1 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 40 Resolution (Bits) 12 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 250 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 210 Architecture Pipeline SNR (dB) 69 ENOB (bit) 11.1 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer No
TQFP (PAG) 64 144 mm² 12 x 12
  • Single +3.0V Supply Operation
  • Internal Sample-and-Hold
  • Internal Reference
  • Outputs 2.4V to 3.6V Compatible
  • Power Down Mode
  • Duty Cycle Stabilizer
  • Multiplexed Output Mode

Key Specifications

  • Resolution 12 Bits
  • DNL ±0.3 LSB (typ)
  • SNR (fIN = 10 MHz) 69 dB (typ)
  • SFDR (fIN = 10 MHz) 85 dB (typ)
  • Data Latency 7 Clock Cycles
  • Power Consumption
    • Operating 210 mW (typ)
    • Power Down Mode 36 mW (typ)

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.

  • Single +3.0V Supply Operation
  • Internal Sample-and-Hold
  • Internal Reference
  • Outputs 2.4V to 3.6V Compatible
  • Power Down Mode
  • Duty Cycle Stabilizer
  • Multiplexed Output Mode

Key Specifications

  • Resolution 12 Bits
  • DNL ±0.3 LSB (typ)
  • SNR (fIN = 10 MHz) 69 dB (typ)
  • SFDR (fIN = 10 MHz) 85 dB (typ)
  • Data Latency 7 Clock Cycles
  • Power Consumption
    • Operating 210 mW (typ)
    • Power Down Mode 36 mW (typ)

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments.

The ADC12DL040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.0V power supply, the ADC12DL040 achieves 11.1 effective bits at nyquist and consumes just 210 mW at 40 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW.

The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC's are available on a single multiplexed 12-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.

To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL040 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage.

This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.

The ADC12DL040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.0V power supply, the ADC12DL040 achieves 11.1 effective bits at nyquist and consumes just 210 mW at 40 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW.

The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC's are available on a single multiplexed 12-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.

To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL040 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage.

This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.

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Technical documentation

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Type Title Date
* Data sheet ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter datasheet (Rev. D) 19 Apr 2013
User guide ADC10DL065/ADC12DL040/ADC12DL065 Instruction Manual 21 Feb 2012
White paper Intermediate Frequency (IF) Sampling Receiver Concepts 31 May 2006
Application note Understanding High-Speed Signals, Clocks, and Data Capture 18 Oct 2005

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ADC12DL040 IBIS Model

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