Product details

Sample rate (Max) (MSPS) 105 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 500 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 374 Architecture Pipeline SNR (dB) 71.5 ENOB (Bits) 11.5 SFDR (dB) 91 Operating temperature range (C) -40 to 85 Input buffer No
Sample rate (Max) (MSPS) 105 Resolution (Bits) 12 Number of input channels 1 Interface type DDR LVDS, Parallel CMOS Analog input BW (MHz) 500 Features Low Power Rating Catalog Input range (Vp-p) 2 Power consumption (Typ) (mW) 374 Architecture Pipeline SNR (dB) 71.5 ENOB (Bits) 11.5 SFDR (dB) 91 Operating temperature range (C) -40 to 85 Input buffer No
VQFN (RHB) 32 25 mm² 5 x 5
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • No External Decoupling Required for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
  • 32-QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems
  • Maximum Sample Rate: 125 MSPS
  • 12-Bit Resolution with No Missing Codes
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference with Support for External Reference
  • No External Decoupling Required for References
  • Programmable Output Clock Position and Drive Strength to Ease Data Capture
  • 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
  • 32-QFN Package (5 mm × 5 mm)
  • Pin Compatible 12-Bit Family (ADS612X)
  • APPLICATIONS
    • Wireless Communications Infrastructure
    • Software Defined Radio
    • Power Amplifier Linearization
    • 802.16d/e
    • Test and Measurement Instrumentation
    • High Definition Video
    • Medical Imaging
    • Radar Systems

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.

It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.

ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.

The devices are specified over the industrial temperature range (-40°C to 85°C).

ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X) is a family of 12-bit A/D converters with sampling frequencies up to 125 MSPS. It combines high performance and low power consumption in a compact 32 QFN package. Using an internal high bandwidth sample and hold and a low jitter clock buffer helps to achieve high SNR and high SFDR even at high input frequencies.

It features coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.

The digital data outputs are either parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, and LVDS current and internal termination programmability.

The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so that the device comes up in the desired state after power-up.

ADS612X includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.

The devices are specified over the industrial temperature range (-40°C to 85°C).

Download

Similar products you might be interested in

open-in-new Compare products
Pin-for-pin with same functionality to the compared device.
ADS6144 ACTIVE 14-Bit, 105-MSPS Analog-to-Digital Converter (ADC) Pin-for-pin 14-bit upgrade

Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TSW1405EVM — Data converter data capture evaluation module with 8 LVDS lanes up to 1.0 Gbps

The TSW1405EVM is a low cost data capture circuit board used to evaluate some of Texas Instruments’ (TI) most popular high speed analog-to-digital converters (ADC).

 

The TSW1405EVM supports a high speed LVDS bus capable of providing 16-bit samples at 1.0 GSPS. The platform supports a 64k sample (...)

Out of stock on TI.com
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADS61xx IBIS Model

SLAC211.ZIP (915 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Calculation tool

ADC-HARMONIC-CALC — Analog-to-digital converter (ADC) harmonic calculator

    The ADC Harmonic Calculation tool is an excel based calculator for determining the location in frequency space of high order harmonics following Nyquist aliasing in an analog to digital converter.

    Given an ADC sample rate and the span of a signal of interest the calcultor will determine if the 2nd (...)

Package Pins Download
VQFN (RHB) 32 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos