CD40106B

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6-ch, 3-V to 18-V inverters with Schmitt-Trigger inputs

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Product details

Parameters

Technology Family CD4000 Supply voltage (Min) (V) 3 Supply voltage (Max) (V) 18 Number of channels (#) 6 IOL (Max) (mA) 2.4 IOH (Max) (mA) -2.4 ICC (Max) (uA) 120 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Standard speed (tpd > 50ns), Input clamp diode Rating Catalog open-in-new Find other Inverting buffers & drivers

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Inverting buffers & drivers

Features

  • Schmitt-Trigger Inputs
  • Hysteresis Voltage (Typical):
    • 0.9 V at VDD = 5 V
    • 2.3 V at VDD = 10 V
    • 3.5 V at VDD = 15 V
  • Noise Immunity Greater Than 50%
  • No Limit On Input Rise and Fall Times
  • Standardized, Symmetrical Output Characteristics
  • For Quiescent Current at 20 V
  • Maximum Input Current Of 1 µA at 18 V Over Full Package Temperature Range:
    • 100 nA at 18 V and 25°C
  • Low VDD and VSS Current During Slow Input Ramp
  • 5-V, 10-V, and 15-V Parametric Ratings
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Description

The CD40106B device consists of six Schmitt-Trigger inputs. Each circuit functions as an inverter with Schmitt-Trigger input. The trigger switches at different points for positive- and negative-going signals. The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH).

The CD40106B device is supplied in ceramic packaging (J) as well as standard packaging (D, N, NS, PW). All CD40106B devices are rated for –55°C to +125°C ambient temperature operation.

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Technical documentation

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Type Title Date
* Data sheet CD40106B CMOS Hex Schmitt-Trigger Inverters datasheet (Rev. F) Mar. 09, 2017
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCHM029A.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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