CD40107B

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CMOS Dual 2-Input NAND Buffer/Driver

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Product details

Parameters

Technology Family CD4000 VCC (Min) (V) 3 VCC (Max) (V) 18 Channels (#) 2 Inputs per channel 2 IOL (Max) (mA) 89 IOH (Max) (mA) 0 Input type Standard CMOS Output type Open-Drain Features Standard Speed (tpd > 50ns) Data rate (Max) (Mbps) 8 Rating Catalog Operating temperature range (C) -55 to 125 open-in-new Find other NAND gate

Package | Pins | Size

PDIP (P) 8 93 mm² 9.81 x 9.43 SOIC (D) 8 19 mm² 3.91 x 4.9 SOP (PS) 8 48 mm² 6.2 x 7.8 TSSOP (PW) 8 19 mm² 3 x 6.4 open-in-new Find other NAND gate

Features

  • 32 times standard B-Series output current drive sinking capability - 136 mA typ. @ VDD = 10 V, VDS = 1 V
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings
  • Noise margin, full package temperature range, RL to VDD = 10 k:
       1 V at VDD = 5 V
       2 V at VDD = 10 V
       2.5 V at VDD = 15 V
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications
    • Driving relays, lamps, LEDs
    • Line driver
    • Level shifter (up or down)
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Description

The CD40107B is a dual 2-input NAND buffer/driver containing two independent 2-input NAND buffers with open-drain single n-channel transistor outputs. This device features a wired-OR capability and high output sink current capability (136 mA typ. at VDD = 10 V, VDS= 1 V). The CD40107B is supplied in 8-lead hermetic dual-in-line ceramic packages (F3A suffix), 8-lead dual-in-line plastic packages (E suffix), 8-lead small-outline packages (M, M96, MT, and PSR suffixes), and 8-lead thin shrink small-outline packages (PW and PWR suffixes).

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Technical documentation

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Type Title Date
* Datasheet CD40107B TYPES datasheet (Rev. D) Oct. 13, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODELS Download
SCHM030.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (P) 8 View options
SO (PS) 8 View options
SOIC (D) 8 View options
TSSOP (PW) 8 View options

Ordering & quality

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