CD4019B CMOS Quad AND/OR Select Gate |

CD4019B (ACTIVE) CMOS Quad AND/OR Select Gate

CMOS Quad AND/OR Select Gate - CD4019B


CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.

The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).


  • Medium speed operation……tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
            1 V at VDD = 5 V
            2 V at VDD = 10 V
         2.5 V at VDD = 15 V
  • Applications:
    • AND-OR select gating
    • Shift-right/shift-left registers
    • True/complement selection
    • AND/OR/Exclusive-OR selection


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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) Inputs per channel IOL (Max) (mA) Input type IOH (Max) (mA) Output type Features Data rate (Max) (Mbps) Rating Operating temperature range (C) Package size: mm2:W x L (PKG) Package Group
CD4019B Order now CD4000     3     18     4     4     6.8     Standard CMOS     -6.8     Push-Pull     Standard Speed (tpd > 50ns)     8     Catalog     -55 to 125     See datasheet (PDIP)
16SO: 80 mm2: 7.8 x 10.2 (SO | 16)
16SOIC: 59 mm2: 6 x 9.9 (SOIC | 16)
16TSSOP: 22 mm2: 4.4 x 5 (TSSOP | 16)    
PDIP | 16
SOIC | 16
SO | 16
TSSOP | 16