CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.
The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Inputs per channel||IOL (Max) (mA)||Input type||IOH (Max) (mA)||Output type||Features||Data rate (Max) (Mbps)||Rating||Operating temperature range (C)||Package size: mm2:W x L (PKG)||Package Group|
||CD4000||3||18||4||4||6.8||Standard CMOS||-6.8||Push-Pull||Standard Speed (tpd > 50ns)||8||Catalog||-55 to 125||
16PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 16)
16SO: 80 mm2: 7.8 x 10.2 (SO | 16)
16SOIC: 59 mm2: 6 x 9.9 (SOIC | 16)
16TSSOP: 22 mm2: 4.4 x 5 (TSSOP | 16)
PDIP | 16
SOIC | 16
SO | 16
TSSOP | 16