CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.
The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Data sheet acquired from Harris Semiconductor
Part number | Order | Technology Family | VCC (Min) (V) | VCC (Max) (V) | Channels (#) | Inputs per channel | IOL (Max) (mA) | IOH (Max) (mA) | Input type | Output type | Features | Data rate (Max) (Mbps) | Rating | Operating temperature range (C) | Package size: mm2:W x L (PKG) | Package Group |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CD4072B |
|
CD4000 | 3 | 18 | 2 | 4 | 6.8 | -6.8 | Standard CMOS | Push-Pull | Standard Speed (tpd > 50ns) | 8 | Catalog | -55 to 125 |
14PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 14)
14SO: 80 mm2: 7.8 x 10.2 (SO | 14) 14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14) 14TSSOP: 32 mm2: 6.4 x 5 (TSSOP | 14) |
PDIP | 14
SOIC | 14 SO | 14 TSSOP | 14 |