Product details
Parameters
Package | Pins | Size
Features
- Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Standardized, symmetrical output characteristics
- Noise margin (full package-temperature range):
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V - 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Data sheet acquired from Harris Semiconductor
Description
CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.
The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
Technical documentation
| Type | Title | Date | |
|---|---|---|---|
| * | Datasheet | CD4071B, CD4072B, CD4075B TYPES datasheet (Rev. D) | Aug. 21, 2003 |
| Selection guides | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
| Application notes | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
| Solution guides | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
| Application notes | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
| User guides | Signal Switch Data Book (Rev. A) | Nov. 14, 2003 | |
| More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
| Application notes | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | Dec. 03, 2001 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Design tools & simulation
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 14 | View options |
| SO (NS) | 14 | View options |
| SOIC (D) | 14 | View options |
| TSSOP (PW) | 14 | View options |
Ordering & quality
Support & training
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Training series
View all TI training and videosVideos
Anatomy of a logic part number
Logic part numbers use a formulaic naming system to denote the device's functionality and features. This video reviews the components to a logic part's name.
