CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSS and ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.
The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Inputs per channel||IOL (Max) (mA)||Input type||IOH (Max) (mA)||Output type||Features||Data rate (Max) (Mbps)||Rating||Operating temperature range (C)||Package size: mm2:W x L (PKG)||Package Group|
||CD4000||3||18||1||2||6.8||Standard CMOS||-6.8||Push-Pull||Standard Speed (tpd > 50ns)||8||Catalog||-55 to 125||
14PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
PDIP | 14
SOIC | 14