CD4086B

ACTIVE

CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

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Product details

Parameters

Technology Family CD4000 VCC (Min) (V) 3 VCC (Max) (V) 18 Channels (#) 1 Inputs per channel 2 IOL (Max) (mA) 6.8 Input type Standard CMOS IOH (Max) (mA) -6.8 Output type Push-Pull Features Standard Speed (tpd > 50ns) Data rate (Max) (Mbps) 8 Rating Catalog Operating temperature range (C) -55 to 125 open-in-new Find other Combination gate

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other Combination gate

Features

  • Medium-speed operation - tPHL = 90 ns; tPLH = 140 ns (typ.) at 10 V
  • INHIBIT and ENABLE inputs
  • Buffered outputs
  • 100% tested for quiescent current at 20 V
  • Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Noise margin (over full package temperature range):
        1 V at VDD = 5 V
        2 V at VDD = 10 V
        2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

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Description

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to VSS and ENABLE/EXP to VDD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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Technical documentation

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Type Title Date
* Datasheet CD4086B TYPES datasheet (Rev. C) Aug. 21, 2003
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics Dec. 03, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

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