The HC03 and HCT03 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads. The HCT logic family is functionally as well as pin compatible with the standard LS logic family.
These open drain NAND gates can drive into resistive loads to output voltages as high as 10V. Minimum values of RL required versus load voltage are shown in Figure 2.
Data sheet acquired from Harris Semiconductor
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Inputs per channel||IOL (Max) (mA)||IOH (Max) (mA)||Input type||Output type||Features||Rating||Data rate (Max) (Mbps)||Operating temperature range (C)||Package size: mm2:W x L (PKG)||Package Group|
||HC||2||6||4||2||5.2||0||Standard CMOS||Open-Drain||High Speed (tpd 10-50ns)||Catalog||28||-55 to 125||
14PDIP: 181 mm2: 9.4 x 19.3 (PDIP | 14)
14SOIC: 52 mm2: 6 x 8.65 (SOIC | 14)
PDIP | 14
SOIC | 14
|CD54HC03||Samples not available||HC||2||6||0||-5.2||Standard CMOS||Push-Pull||Military||-55 to 125||14CDIP: 130 mm2: 6.67 x 19.56 (CDIP | 14)||CDIP | 14|