CD74HC240

ACTIVE

High Speed CMOS Logic Inverting Octal Buffers/Line Drivers with 3-State Outputs

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Product details

Parameters

Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Channels (#) 8 IOL (Max) (mA) 6 IOH (Max) (mA) -6 ICC (Max) (uA) 80 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Data rate (Mbps) 56 Rating Catalog open-in-new Find other Inverting buffer/driver

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 open-in-new Find other Inverting buffer/driver

Features

  • HC/ HCT240 Inverting
  • HC/ HCT241 Non-Inverting
  • HC/ HCT244 Non-Inverting
  • Typical Propagation Delay = 8ns at VCC = 5V, CL = 15pF, TA = 25°C for HC240
  • Three-State Outputs
  • Buffered Inputs
  • High-Current Bus Driver Outputs
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

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Description

The ’HC240 and ’HCT240 are inverting three-state buffers having two active-low output enables. The CD74HC241, ’HCT241, ’HC244 and ’HCT244 are non-inverting three-state buffers that differ only in that the 241 has one active-high and one active-low output enable, and the 244 has two active-low output enables. All three types have identical pinouts.

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Technical documentation

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Type Title Date
* Datasheet CD54/74HC240, CD54/74HCT240, CD74HC241, CD54/74HCT241, CD54 datasheet (Rev. E) Oct. 04, 2004
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Solution guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCHM076.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options

Ordering & quality

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