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CD74HC4016

ACTIVE

12-V, 1:1 (SPST), 4-channel analog switch

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Data sheet

CD74HC4016

ACTIVE
Data sheet Order now

Product details

Configuration 1:1 SPST Number of channels (#) 4 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5, 12 Protocols Analog Ron (Typ) (Ohms) 30 CON (Typ) (pF) 5 Bandwidth (MHz) 200 Operating temperature range (C) -55 to 125 Features Break-before-make Input/output continuous current (Max) (mA) 25 Rating Catalog Supply current (Typ) (uA) 2
Configuration 1:1 SPST Number of channels (#) 4 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5, 12 Protocols Analog Ron (Typ) (Ohms) 30 CON (Typ) (pF) 5 Bandwidth (MHz) 200 Operating temperature range (C) -55 to 125 Features Break-before-make Input/output continuous current (Max) (mA) 25 Rating Catalog Supply current (Typ) (uA) 2
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PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
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  • Wide Analog-Input-Voltage Range . . . 0V to 10V
  • Low "ON" Resistance
    • 45 (Typ) . . . . VCC = 4.5V
    • 35 (Typ) . . . . VCC = 6V
    • 30 (Typ) . .1fcVCC = 9V
  • Fast Switching and Propagation Delay Times
  • Low "OFF" Leakage Current
  • Built-In "Break-Before-Make" Switching
  • Suitable for Sample and Hold Applications
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • HC Types
    • 2V to 10V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • Wide Analog-Input-Voltage Range . . . 0V to 10V
  • Low "ON" Resistance
    • 45 (Typ) . . . . VCC = 4.5V
    • 35 (Typ) . . . . VCC = 6V
    • 30 (Typ) . .1fcVCC = 9V
  • Fast Switching and Propagation Delay Times
  • Low "OFF" Leakage Current
  • Built-In "Break-Before-Make" Switching
  • Suitable for Sample and Hold Applications
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • HC Types
    • 2V to 10V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
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The CD74HC4016 contains four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

Each switch has two input/output terminals (nY, nZ) and an active high enable input (nE). Current through the switch will not cause additional VCC current provided the analog voltage is maintained between VCC and GND.

The CD74HC4016 contains four independent digitally controlled analog switches that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

Each switch has two input/output terminals (nY, nZ) and an active high enable input (nE). Current through the switch will not cause additional VCC current provided the analog voltage is maintained between VCC and GND.

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Technical documentation

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Type Title Date
* Data sheet CD74HC4016 datasheet (Rev. C) 02 Aug 2004
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. D) 09 Dec 2021
Application note Multiplexers and Signal Switches Glossary (Rev. B) 01 Dec 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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PDIP (N) 14 View options
SOIC (D) 14 View options
TSSOP (PW) 14 View options

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