Product details

Technology Family HCT Bits (#) 1 Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull ICC (Max) (uA) 160 IOL (Max) (mA) 4 IOH (Max) (mA) -4
Technology Family HCT Bits (#) 1 Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull ICC (Max) (uA) 160 IOL (Max) (mA) 4 IOH (Max) (mA) -4
PDIP (N) 16 181 mm² 19.3 x 9.4
  • Digital Design Avoids Analog Compensation Errors
  • Easily Cascadable for Higher Order Loops
  • Useful Frequency Range
    • K-Clock...DC to 55MHz (Typ)
    • I/D-Clock...DC to 35MHz (Typ)
  • Dynamically Variable Bandwidth
  • Very Narrow Bandwidth Attainable
  • Power-On Reset
  • Output Capability
    • Standard...XORPDOUT, ECPDOUT
    • Bus Driver...I/DOUT
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • ’HC297 Types
    • Operation Voltage...2 to 6V
    • High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V
  • CD74HCT297 Types
    • Operation Voltage...4.5 to 5.5V
    • Direct LSTTL Input Logic Compatibility VIL =0.8V (Max), VIH =2V (Min)
    • CMOS Input Compatibility II 1µA at VOL , VOH

Data sheet acquired from Harris Semiconductor

  • Digital Design Avoids Analog Compensation Errors
  • Easily Cascadable for Higher Order Loops
  • Useful Frequency Range
    • K-Clock...DC to 55MHz (Typ)
    • I/D-Clock...DC to 35MHz (Typ)
  • Dynamically Variable Bandwidth
  • Very Narrow Bandwidth Attainable
  • Power-On Reset
  • Output Capability
    • Standard...XORPDOUT, ECPDOUT
    • Bus Driver...I/DOUT
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • ’HC297 Types
    • Operation Voltage...2 to 6V
    • High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V
  • CD74HCT297 Types
    • Operation Voltage...4.5 to 5.5V
    • Direct LSTTL Input Logic Compatibility VIL =0.8V (Max), VIH =2V (Min)
    • CMOS Input Compatibility II 1µA at VOL , VOH

Data sheet acquired from Harris Semiconductor

The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).

These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.

The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.

The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.

The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).

These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.

The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.

The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.

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Technical documentation

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Type Title Date
* Data sheet CD54/74HC297, CD74HCT297 datasheet (Rev. B) 16 Apr 2003
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
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PDIP (N) 16 View options

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