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Product details

Parameters

Technology Family HCT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Voltage (Nom) (V) 5 Bits (#) 1 F @ nom voltage (Max) (MHz) 25 ICC @ nom voltage (Max) (mA) 0.08 IOL (Max) (mA) 4 IOH (Max) (mA) -4 Operating temperature range (C) -55 to 125 open-in-new Find other Phase-locked-loop (PLL)/oscillator

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 open-in-new Find other Phase-locked-loop (PLL)/oscillator

Features

  • Digital Design Avoids Analog Compensation Errors
  • Easily Cascadable for Higher Order Loops
  • Useful Frequency Range
    • K-Clock...DC to 55MHz (Typ)
    • I/D-Clock...DC to 35MHz (Typ)
  • Dynamically Variable Bandwidth
  • Very Narrow Bandwidth Attainable
  • Power-On Reset
  • Output Capability
    • Standard...XORPDOUT, ECPDOUT
    • Bus Driver...I/DOUT
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • ’HC297 Types
    • Operation Voltage...2 to 6V
    • High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V
  • CD74HCT297 Types
    • Operation Voltage...4.5 to 5.5V
    • Direct LSTTL Input Logic Compatibility VIL =0.8V (Max), VIH =2V (Min)
    • CMOS Input Compatibility II 1µA at VOL , VOH

Data sheet acquired from Harris Semiconductor

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Description

The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).

These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.

Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.

The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.

The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.

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Technical documentation

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Type Title Date
* Datasheet CD54/74HC297, CD74HCT297 datasheet (Rev. B) Apr. 16, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Technical articles Failure to lock: Why wideband PLL frequency synthesizers lose lock Mar. 22, 2013
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

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PDIP (N) 16 View options

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