Product details

Function Zero-delay Additive RMS jitter (Typ) (fs) 200 Output frequency (Max) (MHz) 125 Number of outputs 16 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 250 Features 1:4 fanout Operating temperature range (C) 0 to 70 Rating Catalog Output type TTL Input type TTL
Function Zero-delay Additive RMS jitter (Typ) (fs) 200 Output frequency (Max) (MHz) 125 Number of outputs 16 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 250 Features 1:4 fanout Operating temperature range (C) 0 to 70 Rating Catalog Output type TTL Input type TTL
TSSOP (DGG) 48 101 mm² 12.5 x 8.1
  • Use CDCVF2510A as a Replacement for this Device
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to Four Banks of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series-Damping Resistors
  • No External RC Network Required Operates at 3.3-V VCC
  • Packaged in Plastic 48-Pin Thin Shrink Small-Outline Package

  • Use CDCVF2510A as a Replacement for this Device
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to Four Banks of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series-Damping Resistors
  • No External RC Network Required Operates at 3.3-V VCC
  • Packaged in Plastic 48-Pin Thin Shrink Small-Outline Package

The CDC2516 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2516 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground.

The CDC2516 is characterized for operation from 0°C to 70°C.

The CDC2516 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2516 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL may be bypassed for test purposes by strapping AVCC to ground.

The CDC2516 is characterized for operation from 0°C to 70°C.

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Technical documentation

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Type Title Date
* Data sheet CDC2516: 3.3-V Phase-Lock Loop Clock Driver datasheet (Rev. C) 02 Dec 2004
Application note High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A) 23 Sep 1998

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