The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC.
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.
EPIC-IIB is a trademark of Texas Instruments Incorporated.
|Part number||Order||Additive RMS jitter (Typ) (fs)||Output frequency (Max) (MHz)||Input level||Number of outputs||Output level||VCC out (V)||Input frequency (Max) (MHz)||Operating temperature range (C)||Rating|
-40 to 85
0 to 70